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PM0044 数据表(PDF) 29 Page - STMicroelectronics |
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PM0044 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 162 page ![]() PM0044 Pipelined execution Doc ID 13590 Rev 3 29/162 5.4.5 Pipeline with 1 wait state In the example given in Table 14, performing the fetch takes 2 cycles, and there is no overlap between the 2 fetch cycles. If the instruction is decoded/executed during the last 2 fetch cycles, then the wait state is transparent compared to the no-wait state execution. Table 14. Pipeline with 1 wait state Address Instruction Decode cycles Execute cycles lgth Time (cycle) 12 34 5 6 7 8 9 10 0xC000 NEG A 1 1 1 MS F1 D E 0xC001 DEC ($10, X) 1 1 3 D E 0xC004 LDW X, #20 1 1 3 MS F2 D E E 0xC007 LD (X), A 1 1 1 D D E 0xC008 INC A 1 1 1 MS F3 D E 0xC009 NEG ($5A, Y) 1 1 1 D E Table 15. Legend Symbol/Color Definition FFetch D Decode stalled DDecode MS Memory stalled EExecute |
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