PM0044 datasheet(22/162 Pages) STMICROELECTRONICS

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Pipelined execution

PM0044

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Doc ID 13590 Rev 3

The op-code is decoded in this stage. When present, the instruction address is used for

address computation, whilst the immediate operand is forwarded to the execution stage.

Long/unaligned instructions

For long instructions (i.e. 5-bytes instructions), the fetch may need 2 program memory

accesses to be completed. In this case, the decoding stage (after decoding the op-code

part), is stalled waiting for the fetch stage to complete the 2nd fetch.

In case of shorter instructions, this may also happen when they cross a 32-bit boundary.

Indirect addressing

For indirect addressing, the CPU is stalled in this stage to read the pointer from the data

memory (i.e. RAM). The number of cycles during which the CPU is stalled depends on the

pointer size (short, long or extended addressing mode).

5.1.3

Execution stage

In the execution stage, the operation is executed and the result is stored in the accumulator,

index register or RAM.

5.2

Data memory conflicts

3 types of operations perform accesses to the data memory:

●

Effective address computation in case of indirect addressing

●

Data read: source operand

●

Data write: destination for store or read-modify-write operations

In case of simultaneous accesses to the same memory area both in execution stage (write)

and decoding stage (read), the decode stage is stalled till the execution stage releases the

resource.

Table 2.

Data/address decoding examples

Instruction

Syntax

Op-code

Data/address

move

LD A, XH

0x95

LD A,($12,SP)

0x7B

0x12

LD ($12,SP),A

0x6B

0x12

Data load / store with

extended address

LDF A,($123456,Y)

0x90 AF

0x12 34 56

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