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AN4471 数据表(PDF) 9 Page - STMicroelectronics |
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AN4471 数据表(HTML) 9 Page - STMicroelectronics |
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9 / 39 page ![]() DocID026197 Rev 1 9/39 AN4471 Hardware layout and configuration 39 Once the FPGA has been configured, the LED DONE (D23) turns on and the FPGA state machine enters the idle state (LED D4 turns on). In order to generate a programmed waveform, the user selects the desired waveform (refer to Section 3.4.1) through the Program button. The selected program is given by the illumination of its corresponding LED (D6, D8, … D21 represent Program 0, Program 1, … Program 15, respectively). Program selection loops back to Program 0 after the last installed program. By pressing the START button, the selected program starts running and the START LED (D2) turns on. When the program ends, the FPGA returns to the IDLE state (LED D4 is on). If a continuous wave program has been selected, the STOP button must be pressed to stop program execution. The FPGA returns to the idle state and the STOP LED (D3) turns on. The LEDs associated with FPGA operations are described in Table 7. The FPGA state machine can be also controlled by an external digital device through the FPGA USER I/O connector (J7), see Table 24 for the naming and pinout positioning of the J35 and J36 Configure J35 and J36 to setup outputs idle state as follows: (default setting: Not Mounted) High Z J35 and J36 unfitted Clamp / TRswitch J35 fitted, J36 unfitted High Z J35 and J36 fitted Clamp J35 unfitted, J36 fitted J37 Configure J37 to connect FPGA outputs to STHV800 (default setting: Not mounted) Fitted: disconnect FPGA outputs (High Z) Unfitted: connect FPGA outputs Table 7. FPGA LED Color Name Description D2 Green START A program is running following activation of the start button SW5. D3 Green STOP The stop button SW4 has been pressed. D4 Green IDLE The FPGA state machine is in the idle state. D5 Red ERROR An error has occurred during FPGA state machine execution. D23 Green DONE The FPGA has been successfully configured. D6-D21 Yellow PROG 0-15 The corresponding program is selected Table 6. FPGA jumper (continued) Description |
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