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UPD75316BGC 数据表(PDF) 25 Page - NEC |
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UPD75316BGC 数据表(HTML) 25 Page - NEC |
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25 / 77 page ![]() Fig. 5-6 Serial Interface Block Diagram fX/2 3 (From Timer/ Event Counter) INTCSI IRQCSI set signal Serial Clock Slector INTCSI Control Circuit RELD Serial Clock Counter Serial Clock Control Circuit P01/SCK P03/SI/SB1 P02/SO/SB0 8/4 CSIM Bit Test 8 8 Internal Bus 8 Slave Address Register (SVA) Addres Comparator Shift Register (SIO) Match Signal RELT Bit Manipulation CMDT SO Latch SET CLR Q D SBIC Bit Test Busy/ Acknowledge Output Circuit (8) (8) (8) CMDD ACKD Bus Release/ Command/ Acknowledge Detector fX/2 4 fX/2 6 TOUT F/F External SCK P01 Output Latch |
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