UPD75316BGC datasheet(9/77 Pages) NEC

9 / 77 page

µPD75312B, 75316B

SYNC *4

X1, X2

XT1

XT2

RESET

VDD

VSS

Function

External event pulse input pin to timer/event counter

Timer/event counter output pin

Clock output pin

Fixed frequency output pin (for buzzer or system clock

trimming)

Serial clock input/output pin

Serial data output pin

Serial bus input/output pin

Serial data input pin

Serial bus input/output pin

Edge detection vectored interrupt input pin (both rising

edge and falling edge detection effective)

Edge detection vectored

interrupt input pin (detection

edge selectable)

Segment signal output pin

Common signal output pin

LCD drive power supply pin

On-chip split resistor (mask option)

External split resistor cut output pin

External expansion driver drive clock output pin

External expansion driver synchronization clock output

Main system clock oscillation crystal/ceramic connection

pin. For external clock, the external clock signal is input

to X1 and the inverted phase is input to X2.

Subsystem clock oscillation crystal connection pin. For

external clock, the external clock signal is input to XT1

and XT2 is opened. XT1 can be used as a 1-bit input

(test) pin.

System reset input pin

Internally Connected. Directly connected to VDD.

Positive power supply pin

GND potential pin

Pin Name

TI0

PTO0

PCL

BUZ

SCK

SO/SB0

SI/SB1

INT4

INT0

S0 to S23

S24 to S31

COM0 to COM3

VLC0 to VLC2

BIAS

LCDCL *4

Dual-

Function Pin

P13

P20

P22

P23

P01

P02

P03

P00

P10

—

BP0 to BP7

—

P30

P31

––

—

Clocked

Asynchronous

Input/Output

Input

Input/output

Input

Output

—

Output

Input/output

Input

—

Input

—

Reset

Input

—

Input

—

––

—

INT1

P11

INT2

Edge detection testable input

pin (rising edge detection)

I/O Circuit

Type *1

B - C

E - B

F - A

F - B

M - C

G - A

G - C

G - B

—

E - B

––

—

KR0 to KR3

Input/output

P60 to P63

Parallel falling edge detection testable input pin

Input

F - A

Input

KR4 to KR7

Input/output

P70 to P73

Parallel falling edge detection testable input pin

F - A

3.2

NON-PORT PINS

Input

P12

Input

B - C

*1.

: Schmitt triggered input

*2. Display outputs are selected with VLCX shown below as the input source.

S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0

However, the level of each display output depends on the display output and VLCX external circuit.

*3. On-chip split resistor………Low level

No on-chip split resistor… High-impedance

*4. Pins provided for system expansion. Currently, only used as P30 and P31 pins.

UPD75316BGC 数据表(PDF) 9 Page - NEC

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UPD75316BGC 数据表(PDF) 9 Page - NEC

UPD75316BGC 数据表(HTML) 9 Page - NEC

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