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UPD75316BGC 数据表(PDF) 59 Page - NEC |
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UPD75316BGC 数据表(HTML) 59 Page - NEC |
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59 / 77 page  59 µPD75312B, 75316B SBI mode (SCK...Internal clock output (master)): (Ta = –40 to +85 °C , VDD = 2.0 to 6.0 V ) VDD = 4.5 to 6.0 V 1600 ns 3800 ns VDD = 4.5 to 6.0 V tKCY3/2–50 ns tKCY3/2–150 ns 250 ns tKCY3/2 ns VDD = 4.5 to 6.0 V 0 250 ns 0 1000 ns tKCY3 ns tKCY3 ns tKCY3 ns tKCY3 ns tKCY3 tKL3 tKH3 tSIK3 tKSI3 tKSO3 SCK cycle time SB0 and SB1 setup time (to SCK ↑) SB0andSB1holdtime (fromSCK ↑) SB0 and SB1 output delay time from SCK ↓ SCK high- and low-level widths SB0, SB1 ↓ from SCK↑ SCK from SB0, SB1 ↓ SB0 and SB1 low-level widths SB0 and SB1 high-level widths tKSB tSBK tSBL tSBH * RL and CL are SB0, SB1 output line load resistance and load capacitance, respectively. SBI mode (SCK...External clock input (slave)): (Ta = –40 to +85 °C , VDD = 2.0 to 6.0 V ) VDD = 4.5 to 6.0 V 800 ns 3200 ns VDD = 4.5 to 6.0 V 400 ns 1600 ns 100 ns tKCY4/2 ns VDD = 4.5 to 6.0 V 0 300 ns 0 1000 ns tKCY4 ns tKCY4 ns tKCY4 ns tKCY4 ns tKCY4 tKL4 tKH4 tSIK4 tKSI4 tKSO4 SCK cycle time SB0 and SB1 setup time (to SCK ↑) SB0andSB1holdtime (fromSCK ↑) SB0 and SB1 output delay time from SCK ↓ SCK high- and low-level widths SB0, SB1 ↓ from SCK↑ SCK from SB0, SB1 ↓ SB0 and SB1 low-level widths SB0 and SB1 high-level widths tKSB tSBK tSBL tSBH * RL and CL are SB0, SB1 output line load resistance and load capacitance, respectively. PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT RL = 1 k Ω, CL = 100 pF* RL = 1 k Ω, CL = 100 pF* |
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