LTC1098AC datasheet(24/28 Pages) LINER

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LTC1096/LTC1096L

LTC1098/LTC1098L

APPLICATI

TYPICAL

Interfacing to the Parallel Port of the

Intel 8051 Family

The Intel 8051 has been chosen to demonstrate the

interface between the LTC1098(L) and parallel port micro-

processors. Normally the CS, CLK and DIN signals would

be generated on three port lines and the DOUT signal read

on a fourth port line. This works very well. However, we

will demonstrate here an interface with the DIN and DOUT

of the LTC1098(L) tied together as described in the

SERIAL INTERFACE section. This saves one wire.

The 8051 first sends the start bit and MUX address to the

LTC1098(L) over the data line connected to P1.2. Then

P1.2 is reconfigured as an input (by writing to it a one) and

the 8051 reads back the 8-bit A/D result over the same

data line.

CLK

DOUT

DIN

LTC1098(L)

ANALOG

INPUTS

P1.4

P1.3

P1.2

8051

MUX ADDRESS

A/D RESULT

LTC1096/8 • TA06

CLK

DATA (DIN/DOUT)

START

ODD/

SIGN

MSBF

MSBF BIT LATCHED

BY LTC1098(L)

LTC1098(L) SENDS A/D RESULT

BACK TO 8051 P1.2

8051 P1.2 OUTPUTS DATA

TO LTC1098(L)

8051 P1.2 RECONFIGURED

AS AN INPUT AFTER THE 4TH RISING

CLK AND BEFORE THE 4TH FALLING CLK

LTC1098(L) TAKES CONTROL OF DATA LINE

ON 4TH FALLING CLK

SGL/

DIFF

LTC1096/8 • TA08

LABEL

MNEMONIC

OPERAND

COMMENTS

MOV

A, #FFH

DIN word for LTC1098(L)

SETB

P1.4

Make sure CS is high

CLR

P1.4

CS goes low

MOV

R4, #04

Load counter

LOOP 1

RLC

Rotate DIN bit into Carry

CLR

P1.3

CLK goes low

MOV

P1.2, C

Output DIN bit to LTC1098(L)

SETB

P1.3

CLK goes high

DJNZ

R4, LOOP 1

Next bit

MOV

P1, #04

Bit 2 becomes an input

CLR

P1.3

CLK goes low

MOV

R4, #09

Load counter

LOOP

MOV

C, P1.2

Read data bit into Carry

RLC

Rotate data bit into Acc.

SETB

P1.3

CLK goes high

CLR

P1.3

CLK goes low

DJNZ

R4, LOOP

Next bit

MOV

R2, A

Store MSBs in R2

SETB

P1.4

CS goes high

DOUT from LTC1098(L) Stored in 8051 RAM

LTC1096/8 • TA07

MSB

LSB

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