LTC3853_15 datasheet(17/36 Pages) LINER

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LTC3853

3853fc

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Inductor Core Selection

Once the inductance value is determined, the type of in-

ductor must be selected. Core loss is independent of core

size for a fixed inductor value, but it is very dependent

on inductance selected. As inductance increases, core

losses go down. Unfortunately, increased inductance

requires more turns of wire and therefore copper losses

will increase.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Power MOSFET and Schottky Diode

(Optional) Selection

Two external power MOSFETs must be selected for each

controller in the LTC3853: one N-channel MOSFET for

the top (main) switch, and one N-channel MOSFET for

the bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTVCC/

DRVCC12 voltage. This voltage is typically 5V during start-

up(seeEXTVCCPinConnection).Consequently,logic-level

threshold MOSFETs must be used in most applications.

The only exception is if low input voltage is expected (VIN

< 5V); then, sub-logic level threshold MOSFETs (VGS(TH)

< 3V) should be used. Pay close attention to the BVDSS

specification for the MOSFETs as well; most of the logic

level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the on-

resistance, RDS(ON), Miller capacitance, CMILLER, input

voltage and maximum output current. Miller capacitance,

CMILLER, can be approximated from the gate charge curve

usually provided on the MOSFET manufacturers’ data

sheet. CMILLER is equal to the increase in gate charge

along the horizontal axis while the curve is approximately

flat divided by the specified change in VDS. This result is

then multiplied by the ratio of the application applied VDS

to the gate charge curve specified VDS. When the IC is

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

Main Switch Duty Cycle

VOUT

VIN

Synchronous Switch Duty Cycle

VIN – VOUT

VIN

The MOSFET power dissipations at maximum output

current are given by:

PMAIN =

VOUT

VIN

IMAX

( )2 1+δ

(

)RDS(ON) +

VIN

( )2

IMAX









RDR

( ) CMILLER

(

)•

VINTVCC – VTH(MIN)

VTH(MIN)













• fOSC

PSYNC =

VIN – VOUT

VIN

IMAX

(

)2 1+δ

(

)RDS(ON)

where

d is the temperature dependency of RDS(ON) and

RDR (approximately 2Ω) is the effective driver resistance

at the MOSFET’s Miller threshold voltage. VTH(MIN) is the

typical MOSFET minimum threshold voltage.

BothMOSFETshaveI2RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For VIN < 20V

the high current efficiency generally improves with larger

MOSFETs, while for VIN > 20V the transition losses rapidly

increase to the point that the use of a higher RDS(ON)device

withlowerCMILLERactuallyprovideshigherefficiency.The

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

The term (1 +

d) is generally given for a MOSFET in the

form of a normalized RDS(ON) vs Temperature curve, but

d = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

APPLICATIONS INFORMATION

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