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LTC3853

3853fc

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The minimum on-time for the LTC3853 is approximately

90ns, with reasonably good PCB layout, minimum 30%

inductor current ripple and at least 10mV to 15mV ripple

on the current sense signal. The minimum on-time can be

affected by PCB switching noise in the voltage and current

loop. However, as the peak sense voltage decreases the

minimum on-time gradually increases to 130ns. This is

of particular concern in forced continuous applications

with low ripple current at light loads. If the duty cycle

drops below the minimum on-time limit in this situation,

a significant amount of cycle skipping can occur with

correspondingly larger current and voltage ripple.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3853 circuits: 1) IC VIN current, 2) INTVCC

regulator current, 3) I2R losses, 4) topside MOSFET

transition losses.

1. The VIN current is the DC supply current given in

the Electrical Characteristics table, which excludes

MOSFET driver and control currents. VIN current typi-

cally results in a small (<0.1%) loss.

2. INTVCC current is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

from INTVCC to ground. The resulting dQ/dt is a cur-

rent out of INTVCC that is typically much larger than the

control circuit current. In continuous mode, IGATECHG

= f(QT + QB), where QT and QB are the gate charges of

the topside and bottom side MOSFETs.

Supplying INTVCC power through EXTVCC from an

output-derivedsourcewillscaletheVINcurrentrequired

for the driver and control circuits by a factor of (Duty

Cycle)/(Efficiency). For example, in a 20V to 5V applica-

tion, 10mA of INTVCC current results in approximately

2.5mA of VINcurrent.Thisreducesthemid-currentloss

from 10% or more (if the driver was powered directly

from VIN) to only a few percent.

3. I2R losses are predicted from the DC resistances of the

fuse(ifused),MOSFET,inductor,currentsenseresistor.

In continuous mode, the average output current flows

through L and RSENSE, but is “chopped” between the

topside MOSFET and the synchronous MOSFET. If the

two MOSFETs have approximately the same RDS(ON),

then the resistance of one MOSFET can simply be

summed with the resistances of L and RSENSE to obtain

I2R losses. For example, if each RDS(ON) = 10mΩ, RL

= 10mΩ, RSENSE = 5mΩ, then the total resistance is

25mΩ. This results in losses ranging from 2% to 8%

as the output current increases from 3A to 15A for

a 5V output, or a 3% to 12% loss for a 3.3V output.

Efficiency varies as the inverse square of VOUT for the

same external components and output power level. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

4. Transition losses apply only to the topside MOSFET(s),

and become significant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

Transition Loss = (1.7) VIN2 IO(MAX) CRSS f

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is

very important to include these “system” level losses

during the design phase. The internal battery and fuse

resistance losses can be minimized by making sure that

CIN has adequate charge storage and very low ESR at the

switching frequency. A 25W supply will typically require a

minimum of 20µF to 40µF of capacitance having a maxi-

mum of 20mΩ to 50mΩ of ESR. The LTC3853 3-phase

architecturereducesthisinputcapacitancerequirementup

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