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LTC1853 数据表(PDF) 24 Page - Linear Technology |
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LTC1853 数据表(HTML) 24 Page - Linear Technology |
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24 / 24 page  LTC1852/LTC1853 24 18523fa Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2001 LT 0108 REV A • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTC1410 12-Bit, 1.25Msps, ± 5V ADC 71.5dB SINAD at Nyquist, 150mW Dissipation LTC1415 12-Bit, 1.25Msps, Single 5V ADC 55mW Power Dissipation, 72dB SINAD LTC1418 14-Bit, 200ksps, Single 5V ADC 15mW, Serial/Parallel ±10V LTC1419 Low Power 14-Bit, 800ksps ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation LTC1604 16-Bit, 333ksps, ±5V ADC 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608 LTC1850/LTC1851 10-Bit/12, 8-Channel, 1.25Msps ADCs Pin-Compatible, Programmable Multiplexer and Sequencer Data buffering using two IDT7202LA15 1k x 9-bit FIFOs allows rapid collection of 1024 samples and simple interface to low power, low speed, 8-bit microcontrollers. Data and channel information are clocked in simultaneously and read out as two bytes using READ HIGH FIFO and READ LOW FIFO lines. In the event of bus contention, resistors limit peak output current. If both FIFOs are read completely or reset before a burst of conversions, the empty, half full, and full flags from only one FIFO need to be monitored. The retransmit inputs may also be tied together. Retransmit may be used to read data repeatedly, allowing a memory limited processor to perform transform and filtering func- tions that would otherwise be difficult. BUSY DIFFOUT/S6 A2OUT/S5 A1OUT/S4 A0OUT/S3 D11/S2 D10/S1 D9/S0 D8 D7 D6 D5 D4 D3 D2 D1 D0 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M1 M0 SHDN CS CONVST RD WR DIFF A2 A1 A0 UNI/BIP PGA 48 36 47 46 45 44 43 42 41 40 39 38 37 OGND 34 18523 TA03 OVDD 35 1.6384X REFCOMP REFIN REFOUT 12 11 10 2.5V 4.096V COM CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 14 VDD 9 8 7 6 5 4 3 2 1 INPUT CONFIGURATION: ALL 8 CHANNELS SINGLE ENDED TO COM CH0–CH7: 0V TO 4.096V 15 0.1μF VDD 5V 10μF GND GND 13 16 1μF 0.1μF 10μF 0.1μF 10μF 5V 5V 5V 5V *CONVERT CLOCK OUTPUT DRIVERS DATA LATCHES REF AMP 8-CHANNEL MULTIPLEXER 2.5V REFERENCE INTERNAL CLOCK LTC1853 CONTROL LOGIC AND PROGRAMMABLE SEQUENCER 12-BIT SAMPLING ADC + – D8 D7 D6 D5 D4 D3 D2 D1 D0 WR FF RS D7 D6 D5 D4 D3 D2 D1 D0 2 24 25 26 27 3 4 5 6 1 8 22 13 18 18 17 16 12 11 10 9 15 21 20 23 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 R EF HF RT XI GND READ_HIGH_FIFO HIGH_FIFO_EMPTY HIGH_FIFO_HALF_FULL HIGH BYTE_FIFO_RETRANSMIT 7 14 28 0.1μF 5V 8 × 1k HIGH_FIFO_FULL_FLAG LOW_FIFO_FULL_FLAG FIFO_RESET D8 D7 D6 D5 D4 D3 D2 D1 D0 WR FF RS 2 24 25 26 27 3 4 5 6 1 8 22 13 19 18 17 16 12 11 10 9 15 21 20 23 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 R EF HF RT XI GND READ_LOW_FIFO LOW_FIFO_EMPTY LOW_FIFO_HALF_FULL LOW BYTE_FIFO_RETRANSMIT 7 14 28 0.1μF 5V 8 × 1k 8-BIT DATA BUS IDT7202LA15 IDT7202LA15 UP TO 1024 |
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