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932SQL450 数据表(PDF) 17 Page - Integrated Device Technology

部件名 932SQL450
功能描述  Integrated 85 ohm differential terminations
PDF  23 Pages
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制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology

932SQL450 数据表(HTML) 17 Page - Integrated Device Technology

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REVISION B 03/06/15
17
LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES
932SQL450 DATASHEET
Electrical Characteristics–REF14M
Test Clarification Table
TA = 0 - 70°C; Supply Voltage VDD/VDDA = 3.3 V +/-5%,
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Output Impedance
RDSP
VO = VDD*(0.5)
12
21.7
55
Ω
1
Output High Voltage
VOH
IOH = -1 mA
2.4
V
Output Low Voltage
VOL
IOL = 1 mA
0.55
V
Clock High Time
THIGH
1.5V
27.5
ns
1
Clock Low Time
TLOW
1.5V
27.5
ns
1
Edge Rate
tslewr/f
Rising/Falling edge rate
1
1.9
4
V/ns
1,2
Duty Cycle
dt1
VT = 1.5 V
45
50.1
55
%
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
42
1000
ps
1
See "Power Supply and Test Loads" page for termination circuits
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured between 0.8V and 2.0V
Comments
TEST_SEL
HW PIN
TEST_MOD
E
HW PIN
TEST
ENTRY BIT
B6b6
REF/N or
HI-Z
B6b7
OUTPUT
0
X
0
X
NORMAL
10
X
0
HI-Z
10
X
1
REF/N
11
X
0
REF/N
11
X
1
REF/N
0X
1
0
HI-Z
0X
1
1
REF/N
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
HW
SW
Power-up w/ TEST_SEL = 1 (>0.7V) to enter test
mode. Cycle power to disable test mode.
If TEST_SEL HW pin is 0 during power-up,
test mode can be selected through B6b6.
If test mode is selected by B6b6, then B6b7
is used to select HI-Z or REF/N
FS_B/TEST_Mode pin is not used.
Cycle power to disable test mode.



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