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932SQL450 数据表(PDF) 12 Page - Integrated Device Technology |
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932SQL450 数据表(HTML) 12 Page - Integrated Device Technology |
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12 / 23 page ![]() LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 12 REVISION B 03/06/15 932SQL450 DATASHEET SMBus Table: NS_SAS/NS_SRC Frequency Margining Table Pin # Name Control Function Type 0 1 Default Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 FS3 Freq. Sel 3 RW 0 Bit 2 FS2 Freq. Sel 2 RW 1 Bit 1 FS1 Freq. Sel 1 RW 1 Bit 0 FS0 Freq. Sel 0 RW 1 SMBus Table: Test Mode and CPU/SRC/PCI Frequency Select Register Pin # Name Control Function Type 0 1 Default Bit 7 Test Mode Test Mode Type RW Hi-Z REF/N 0 Bit 6 Test Select Select Test Mode RW Disable Enable 0 Bit 5 0 Bit 4 1 Bit 3 0 Bit 2 FS2 Freq. Sel 2 RW 0 Bit 1 FS1 Freq. Sel 1 RW 1 Bit 0 FS0 Freq. Sel 0 RW 1 Note: Internal Pull up on 100M_133M# pin will result in default CPU frequency of 100 MHz. SMBus Table: Vendor & Revision ID Register Pin # Name Control Function Type 0 1 Default Bit 7 RID3 R 0 Bit 6 RID2 R 0 Bit 5 RID1 R 0 Bit 4 RID0 R 1 Bit 3 VID3 R 0 Bit 2 VID2 R 0 Bit 1 VID1 R 0 Bit 0 VID0 R 1 SMBus Table: Byte Count Register Pin # Name Control Function Type 0 1 Default Bit 7 BC7 RW 0 Bit 6 BC6 RW 0 Bit 5 BC5 RW 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW 0 Bit 2 BC2 RW 0 Bit 1 BC1 RW 0 Bit 0 BC0 RW 1 SMBus Table: Device ID Register Pin # Name Control Function Type 0 1 Default Bit 7 DID7 R -- 0 Bit 6 DID6 R -- 1 Bit 5 DID5 R -- 0 Bit 4 DID4 R -- 0 Bit 3 DID3 R -- 0 Bit 2 DID2 R -- 1 Bit 1 DID1 R -- 0 Bit 0 DID0 R -- 1 - - - - - See CPU/SRC/PCI Frequency Select Table RESERVED - 1 for B rev 0001 for ICS/IDT - Byte 9 - - Byte 5 - Byte 6 - - - RESERVED REVISION ID (1h forB rev) See NS_SAS/NS_SRC Frequency Table. RESERVED Byte 7 - - - - Byte 8 - - - - - - RESERVED - - - - RESERVED - RESERVED Device ID (45 hex) Byte Count Programming b(7:0) Writing to this register will configure how many bytes will be read back, default is A bytes. (0 to 9 VENDOR ID RESERVED |
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