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932SQL450 数据表(PDF) 16 Page - Integrated Device Technology

部件名 932SQL450
功能描述  Integrated 85 ohm differential terminations
PDF  23 Pages
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制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology

932SQL450 数据表(HTML) 16 Page - Integrated Device Technology

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LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES
16
REVISION B 03/06/15
932SQL450 DATASHEET
Electrical Characteristics–Phase Jitter Parameters
Electrical Characteristics–PCI
TA = 0 - 70°C; Supply Voltage VDD/VDDA = 3.3 V +/-5%,
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
INDUST.
LIMIT
UNITS Notes
tjphPCIeG1
PCIe Gen 1
35
39
86
ps (p-p)
1,2,3,
6
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
1.52
1.84
3
ps
(rms)
1,2,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.19
2.42
3.1
ps
(rms)
1,2,6
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR =
10MHz)
0.51
0.59
1
ps
(rms)
1,2,4,
6
QPI & SMI
(100MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.25
0.37
0.5
ps
(rms)
1,5,7
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
0.18
0.23
0.3
ps
(rms)
1,5,7
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.15
0.19
0.2
ps
(rms)
1,5,7
tjphSAS12G
SAS 12G
1.15
1.27
1.3
ps
(rms)
1,5,8
1 Guaranteed by design and characterization, not 100% tested in production.
6 Applied to SRC outputs
7 Applies to CPU outputs
8 Applies to NS_SAS, NS_SRC outputs, Spread Off
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Subject to final radification by PCI SIG.
5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.6
Phase Jitter
tjphPCIeG2
tjphQPI_SMI
2 See http://www.pcisig.com for complete specs
TA = 0 - 70°C; Supply Voltage VDD/VDDA = 3.3 V +/-5%,
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Output Impedance
RDSP
VO = VDD*(0.5)
12
22
55
Ω
1
Output High Voltage
VOH
IOH = -1 mA
2.4
V
Output Low Voltage
VOL
IOL = 1 mA
0.55
V
Clock High Time
THIGH
1.5V
12
ns
1
Clock Low Time
TLOW
1.5V
12
ns
1
Edge Rate
tslewr/f
Rising/Falling edge rate
1
1.7
4
V/ns
1,2
Duty Cycle
dt1
VT = 1.5 V
45
50.4
55
%
1
Group Skew
tskew
VT = 1.5 V
197
500
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
45.52
500
ps
1
See "Power Supply and Test Loads" page for termination circuits
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured between 0.8V and 2.0V



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