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932SQL450 数据表(PDF) 15 Page - Integrated Device Technology |
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932SQL450 数据表(HTML) 15 Page - Integrated Device Technology |
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15 / 23 page  REVISION B 03/06/15 15 LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 932SQL450 DATASHEET DC Electrical Characteristics–Differential LP-HCSL Outputs (CPU, SRC, NS_SAS, NS_SRC, DOT96) Electrical Characteristics–48MHz TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Slew rate dV/dt Scope averaging on 1.5 2.9 4 V/ns 1,2,3 Slew rate matching ∆dV/dt Slew rate matching, Scope averaging on 520 % 1,2,4 Voltage High VHigh 660 774 850 Voltage Low VLow -150 83 150 Max Voltage Vmax 918 1150 7 Min Voltage Vmin -300 -3 7 Vswing Vswing Scope averaging off 300 1359 mV 1,2 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 432 550 mV 1,5 Crossing Voltage (var) ∆-Vcross Scope averaging off 14 140 mV 1,6 2 Measured from differential waveform 7 Includes overshoot and undershoot. 8 Measured from single-ended waveform 9 Measured with scope averaging off, using statistics function. Variation is difference between min and max. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. Statistical measurement on single- ended signal using oscilloscope math function. (Scope averaging on) mV Measurement on single ended signal using absolute value. (Scope mV 1Guaranteed by design and characterization, not 100% tested in production. Z O=85Ω (differential impedance). 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. TA = 0 - 70°C; Supply Voltage VDD/VDDA = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Output Impedance RDSP VO = VDD*(0.5) 12 21.7 55 Ω 1 Output High Voltage VOH IOH = -1 mA 2.4 V Output Low Voltage VOL IOL = 1 mA 0.55 V Clock High Time THIGH 1.5V 8.094 10.036 ns 1 Clock Low Time TLOW 1.5V 7.694 9.836 ns 1 Edge Rate tslewr/f_USB Rising/Falling edge rate 1 2.3 V/ns 1,2 Duty Cycle dt1 VT = 1.5 V 45 50.4 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 350 ps 1 See "Power Supply and Test Loads" page for termination circuits 1Guaranteed by design and characterization, not 100% tested in production. 2 Measured between 0.8V and 2.0V |
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