DATA SHEET

ICS831752AGI REVISION A JUNE 28, 2012

1

©2012 Integrated Device Technology, Inc.

Clock Switch for ATCA/AMC and

PCIe Applications

ICS831752I

General Description

The ICS831752I is a high-performance, differential HCSL clock

switch. The device is designed for the routing of PCIe clock signals in

ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen

3. The device has one differential, bi-directional I/O (FCLK) for

connection to ATCA clock sources and to clock receivers through a

connector. The differential clock input CLK is the local clock input and

the HCSL output Q is the local clock output. In the common clock

mode, FCLK serves as an input and is routed to the differential HCSL

output Q. There are two local clock modes. In the local clock mode 0,

CLK is the input, Q is the clock output and FCLK is in high-impedance

state. In the local clock mode 1, CLK is the input and both Q and

FCLK are the outputs of the locally generated PCIe clock signal. The

ICS831752I is characterized to operate from a 3.3V power or 2.5V

power supply. The ICS831752I supports the switching of PCI Express

(2.5 Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock signals.

Features

- When operating as an output, FCLK is a source-terminated

HCSL signal.

- When operating as an input, FCLK accepts HCSL, LVDS and

LVPECL levels.

differential signals

compliant

ICS831752I

16-lead TSSOP

4.4mm x 5.0mm x 0.925mmpackage body

G Package, Top View

Pin Assignment

16

IREF

15

GND

14

VDD

13

Q

12

nQ

11

GND

10

VDD

9

nc

DIR_SEL

1

nOEFCLK

2

VDD

3

FCLK

4

nFCLK

5

GND

6

CLK

7

nCLK

8

Block Diagram

Pulldown

Pullup/Pulldown

Pullup

Pulldown

FCLK

nFCLK

CLK

nCLK

nOEFCLK

DIR_SEL

IREF

1

0

Q

nQ

1=disable

50

50

50

50

22.33

22..33