ICS831752I Data Sheet

CLOCK SWITCH FOR ATCA/AMC AND PCIe APPLICATIONS

ICS831752AGI REVISION A JUNE 28, 2012

10

©2012 Integrated Device Technology, Inc.

3.3V Differential Clock Input Interface

The CLK/nCLK accepts HCSL, LVDS and LVPECL and other

for the CLK/nCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. If the driver is

from another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements. The figures below also apply to FCLK/

nFCLK operating as an input.

Figure 3A. CLK/nCLK Input Driven by a 3.3V LVPECL

Driver

Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL

Driver

Figure 3E. CLK/nCLK Input Driven by a 3.3V LVDS Driver

Figure 3B. CLK/nCLK Input Driven by a 3.3V HCSL Driver

Figure 3D. CLK/nCLK Input Driven by a 3.3V LVPECL

Driver with AC Couple

CLK

nCLK

Differential

Input

LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

R1

50

Ω

R2

50

Ω

R2

50

Ω

R3

125

R4

125

R1

84

R2

84

3.3V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

3.3V

LVPECL

Differential

Input

3.3V

R1

100

LVDS

CLK

nCLK

3.3V

Differential

Input

Zo = 50

Ω

Zo = 50

Ω

HCSL

*R3

33

Ω

*R4

33

Ω

CLK

nCLK

3.3V

3.3V

Zo = 50

Ω

Zo = 50

Ω

Differential

Input

R1

50

Ω

R2

50

Ω

*Optional – R3 and R4 can be 0

Ω