PIC16C925T-SSLASHCL datasheet(61/182 Pages) MICROCHIP

61 / 182 page

 2001 Microchip Technology Inc.

Preliminary

DS39544A-page 59

PIC16C925/926

9.0

SYNCHRONOUS SERIAL PORT

(SSP) MODULE

The Synchronous Serial Port (SSP) module is a serial

interface useful for communicating with other periph-

eral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The SSP module can

operate in one of two modes:

• Serial Peripheral Interface (SPITM)

• Inter-Integrated Circuit (I2CTM)

Refer to Application Note AN578, "Use of the SSP

Module in the I 2C Multi-Master Environment.”

SSPSTAT: SERIAL PORT STATUS REGISTER (ADDRESS 94h)

R/W-0

R-0

SMP

CKE

D/A

R/W

bit 7

bit 0

bit 7

SMP: SPI Data Input Sample Phase bit

SPI Master mode:

= Input data sampled at end of data output time

= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

bit 6

CKE: SPI Clock Edge Select bit (see Figure 9-3, Figure 9-4, and Figure 9-5)

CKP = 0:

= Data transmitted on rising edge of SCK

= Data transmitted on falling edge of SCK

CKP = 1:

= Data transmitted on falling edge of SCK

= Data transmitted on rising edge of SCK

bit 5

D/A: Data/Address bit (I2C mode only)

= Indicates that the last byte received or transmitted was data

= Indicates that the last byte received or transmitted was address

bit 4

P: STOP bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the START

bit was detected last.)

= Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)

= STOP bit was not detected last

bit 3

S: START bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the STOP

bit was detected last.)

= Indicates that a START bit has been detected last (this bit is ’0’ on RESET)

= START bit was not detected last

bit 2

R/W: Read/Write bit Information (I2C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next START bit, STOP bit, or ACK bit.

= Read

= Write

bit 1

UA: Update Address (10-bit I2C mode only)

= Indicates that the user needs to update the address in the SSPADD register

= Address does not need to be updated

bit 0

BF: Buffer Full Status bit

Receive (SPI and I2C modes):

= Receive complete, SSPBUF is full

= Receive not complete, SSPBUF is empty

Transmit (I2C mode only)

= Transmit in progress, SSPBUF is full

= Transmit complete, SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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