PIC16C925T-SSLASHCL datasheet(109/182 Pages) MICROCHIP

109 / 182 page

 2001 Microchip Technology Inc.

Preliminary

DS39544A-page 107

PIC16C925/926

12.5

Interrupts

The PIC16C925/926 family has nine sources of

interrupt:

• External interrupt RB0/INT

• TMR0 overflow interrupt

• PORTB change interrupts

(pins RB7:RB4)

• A/D Interrupt

• TMR1 overflow interrupt

• TMR2 matches period interrupt

• CCP1 interrupt

• Synchronous serial port interrupt

• LCD module interrupt

The interrupt control register (INTCON) records individ-

ual interrupt requests in flag bits. It also has individual

and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>),

enables (if set) all unmasked interrupts, or disables (if

cleared) all interrupts. When bit GIE is enabled, and an

interrupt’s flag bit and mask bit are set, the interrupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous

registers.

Individual

interrupt

bits

are

set,

regardless of the status of the GIE bit. The GIE bit is

cleared on RESET.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine as well as sets the GIE bit, which

re-enables interrupts.

The RB0/INT pin interrupt, the RB port change interrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

The peripheral interrupt flags are contained in the spe-

cial function register, PIR1. The corresponding inter-

rupt enable bits are contained in special function

contained in special function register, INTCON.

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupts, the return

address is pushed onto the stack and the PC is loaded

with 0004h. Once in the Interrupt Service Routine the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as the RB0/INT pin

or RB Port change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends

when

the

interrupt

event

occurs

(Figure 12-11). The latency is the same for one or two

cycle instructions. Individual interrupt flag bits are set,

regardless of the status of their corresponding mask

bit, PEIE bit, or the GIE bit.

FIGURE 12-10:

INTERRUPT LOGIC

Note:

Individual interrupt flag bits are set, regard-

less of the status of their corresponding

mask bit, or the GIE bit.

TMR1IF

TMR1IE

TMR2IF

TMR2IE

CCP1IF

CCP1IE

LCDIF

LCDIE

SSPIF

SSPIE

TMR0IF

TMR0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

PEIF

ADIF

ADIE

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