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ams Datasheet

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[v1-02] 2014-Oct-29

AS5601 − Detailed Description

I²C Timing

Figure 14:

I²C Timing

Note(s) and/or Footnote(s):

1. After this time, the first clock is generated.

to bridge the undefined region of the falling edge of SCL.

the device does not stretch the low phase of SCL. If such a device does stretch the low phase of SCL, it must drive the next data bit

4. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, this has to be

considered for bus timing.

Symbol

Parameter

Conditions

Min

Max

Units

SCL clock frequency

1.0

MHz

Bus free time (time

between the STOP and

START conditions)

0.5

μs

Hold time; (Repeated)

START condition (1)

0.26

μs

Low phase of SCL clock

0.5

μs

High phase of SCL clock

0.26

μs

Setup time for a

Repeated START

condition

0.26

μs

Data hold time (2)

0.45

μs

Data setup time (3)

50

ns

Rise time of SDA and SCL

signals

120

ns

Fall time of SDA and SCL

signals

10

120 (4)

ns

Setup time for STOP

condition

0.26

μs