AS5601-ASOT datasheet(13/43 Pages) AMSCO

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[v1-02] 2014-Oct-29

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AS5601 − Detailed Description

I²C Modes

Invalid Addresses

There are two addresses used to access an AS5601 register. The

first is the slave address used to select the AS5601. All I²C bus

transactions include a slave address. The slave address of the

AS5601 is 0x36 (0110110 in binary). The second address is a

word address sent in the first byte transferred in a write

transaction. The word address selects a register on the AS5601.

The word address is loaded into the address pointer on the

AS5601. During subsequent read transactions and subsequent

bytes in the write transaction, the address pointer provides the

address of the selected register. The address pointer is

incremented after each byte is transferred, except for certain

read transactions to special registers.

If the user sets the address pointer to an invalid word address,

the address byte is not acknowledged (the A bit is high).

Nevertheless, a read or write cycle is possible. The address

pointer is increased after each byte.

Reading

When reading from an invalid address, the AS5601 returns all

zeros in the data bytes. The address pointer is incremented after

each byte. Sequential reads over the whole address range are

possible including address overflow.

Automatic increment of the address pointer for ANGLE, RAW

ANGLE, and MAGNITUDE registers:

These are special registers which suppress the automatic

increment of the address pointer on reads, so a re-read of these

registers requires no I²C write command to reload the address

pointer. This special treatment of the pointer is effective only if

the address pointer is set to the higher byte of the register,

which holds the least significant bits.

Writing

A write to an invalid address is not acknowledged by the

AS5601, although the address pointer is incremented. When the

address pointer points to a valid address again, a successful

write accessed is acknowledged. Page write over the whole

address range is possible including address overflow.

Supported bus protocol

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever

SCL is high. Changes in the data line while SCL is high are

interpreted as START or STOP conditions.

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