AS5601-ASOT datasheet(14/43 Pages) AMSCO

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[v1-02] 2014-Oct-29

AS5601 − Detailed Description

Accordingly, the following bus conditions have been defined:

Bus Not Busy

Both SDA and SCL remain high.

Start Data Transfer

A change in the state of SDA from high to low while SCL is high

defines the START condition.

Stop Data Transfer

A change in the state of SDA from low to high while SCL is high

defines the STOP condition.

Data Valid

The state of the data line represents valid data when, after a

START condition, SDA is stable for the duration of the high

phase of SCL. The data on SDA must only be changed during

the low phase of SCL. There is one clock period per bit of data.

Each I²C bus transaction is initiated with a START condition and

terminated with a STOP condition. The number of data bytes

transferred between START and STOP conditions is not limited,

and is determined by the I²C bus master. The information is

transferred byte-wise and each receiver acknowledges with a

ninth bit.

Acknowledge

Each I²C slave device, when addressed, is obliged to generate

an acknowledge after the reception of each byte. The I²C bus

master device must generate an extra clock period for this

acknowledge bit.

A slave that acknowledges must pull down SDA during the

acknowledge clock period in such a way that SDA is stable low

during the high phase of the acknowledge clock period. Of

course, setup and hold times must be taken into account. A

master must signal an end of a read transaction by not

generating an acknowledge bit on the last byte that has been

clocked out of the slave. In this case, the slave must leave SDA

high to enable the master to generate the STOP condition.

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