USB5533B datasheet(19/71 Pages) MICROCHIP

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 2012 - 2015 Microchip Technology Inc.

DS00001680C-page 19

USB5533B

4.2.1.1

Invalid Protocol Response Behavior

Note that any attempt to update registers with an invalid protocol will not be updated. The only valid protocols are write

block and read block (described Section 5.5, "SMBus Slave Interface," on page 29), where the hub only responds to the

7-bit hardware selected slave addresses (0101100b or 0101101b). Additionally, the only valid registers for the hub are

outlined in the USB5533B Configuration Release Notes documentation.

4.2.2

SLAVE DEVICE TIMEOUT

Devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds

25 ms (TTIMEOUT, MIN). The master must detect this condition and generate a stop condition within or after the transfer

of the interrupted data byte. Slave devices must reset their communication and be able to receive a new START condi-

tion no later than 35 ms (TTIMEOUT, MAX).

4.2.3

STRETCHING THE SCLK SIGNAL

The hub supports stretching of the SCLK by other devices on the SMBus. The hub will stretch the clock as needed.

4.2.4

BUS RESET SEQUENCE

The SMBus slave interface resets and returns to the idle state upon a START condition followed immediately by a STOP

condition.

4.2.5

SMBUS ALERT RESPONSE ADDRESS

The SMBALERT# signal is not supported by the USB5533B.

FIGURE 4-10:

SMBUS SLAVE CONNECTION

Note:

Some simple devices do not contain a clock low drive circuit; this simple kind of device typically resets its

communications port after a start or stop condition. The slave device timeout must be implemented.

Master

SM_CLK

SM_DAT

SCL

SDA

VDD

10 k



USB Hub

10 k



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