USB5533B datasheet(20/71 Pages) MICROCHIP

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USB5533B

DS00001680C-page 20

 2012 - 2015 Microchip Technology Inc.

4.3

Reset

There are two different resets that the device experiences. One is a hardware reset (either from the internal POR reset

circuit or via the RESET_N pin) and the second is a USB Bus Reset.

4.3.1

INTERNAL POR

All reset timing parameters are guaranteed by design.

4.3.2

EXTERNAL HARDWARE RESET

A valid hardware reset is defined as assertion of RESET_N for a minimum of 1

s after all power supplies are within

operating range.

Assertion of RESET_N (external pin) causes the following:

The PHY is disabled, and the differential pairs will be in a high-impedance state.

All transactions immediately terminate; no states are saved.

All internal registers return to the default state.

The external crystal oscillator is halted.

The PLL is halted.

4.4

Standard Port Power Configuration

The device natively operates with standard port power controllers or poly-fuse devices for the downstream port powers

when battery charging is not enabled on a port. It is not recommended to have the downstream ports of a single device

mix poly-fuse and standard power controller support, as the configuration of the hub cannot correctly report which ports

are poly-fuse and which are port power controllers to the host.

Any port without battery charging can also be used in individual port power controls or ganged power controls. The port

power control output only supports either Ganged or Individual modes on a global basis for all downstream ports.

The overcurrent setting also supports individual or global settings, but also adds the ability to configure specific ports to

be part of an overcurrent gang with others setup for individual connections. This hybrid configuration should only be

used when utilizing poly-fuse power devices.

4.4.1

PORT POWER CONTROLLER

The most common method for downstream port power controls is to utilize current-limited power switches for USB appli-

cations. The devices allow the downstream port powers to be enabled through a control signal and report over-current

conditions through a flag output.

Two connection methods are possible for these controllers, Combined mode and Independent mode.

In Combined mode, the FLG and EN signals are tied together with an external 10K ohm pull-up and driven to a single

PRT_CTL signal on the device, as shown in Figure 4-11.

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