USB3300 datasheet(33/53 Pages) MICROCHIP

33 / 53 page

 2014-2015 Microchip Technology Inc.

DS00001783B-page 33

USB3300

6.1.11

RESET PIN

The reset input of the USB3300 may be asynchronously asserted and de-asserted so long as it is held in the asserted

state continuously for a duration greater than one clkout clock cycle. The reset input may be asserted when the

USB3300 clkout signal is not active (i.e. in the suspend state caused by asserting the SuspendM bit) but reset must only

be de-asserted when the USB3300 clkout signal is active and the reset has been held asserted for a duration greater

than one clkout clock cycle. No other PHY digital input signals may change state for two clkout clock cycles after the de-

assertion of the reset signal.

6.2

Hi-Speed USB Transceiver

The Microchip Hi-Speed USB 2.0 Transceiver consists of four blocks in the lower right corner of Figure 6-1, "Simplified

USB3300 Architecture". These four blocks are labeled HS XCVR, FS/LS XCVR, Resistors, and Bias Gen.

6.2.1

HIGH SPEED AND FULL SPEED TRANSCEIVERS

The USB3300 transceiver meets all requirements in the USB 2.0 specification.

The receivers connect directly to the USB cable. This block contains a separate differential receiver for HS and FS

mode. Depending on the mode, the selected receiver provides the serial data stream through the multiplexer to the RX

Logic block. The FS mode section of the FS/HS RX block also consists of a single-ended receiver on each of the data

lines to determine the correct FS linestate. For HS mode support, the FS/HS RX block contains a squelch circuit to

insure that noise is never interpreted as data.

The transmitters connect directly to the USB cable. The block contains a separate differential FS and HS transmitter

which receive encoded, bit stuffed, serialized data from the TX Logic block and transmit it onto the USB cable.

6.2.2

TERMINATION RESISTORS

The USB3300 transceiver fully integrates all of the USB termination resistors. The USB3300 includes 1.5kΩ pull-up

resistors on both DP and DM and a 15kΩ pull-down resistor on both DP and DM. The 45Ω high speed termination resis-

tors are also integrated. These resistors require no tuning or trimming by the Link. The state of the resistors is deter-

mined by the operating mode of the PHY. The possible valid resistor combinations are shown in Table 6-8, "DP/DM

Termination vs. Signaling Mode". Operation is guaranteed in the configurations given in the table below.

• RPU_DP_EN activates the 1.5kΩ DP pull-up resistor

• RPU_DM_EN activates the 1.5kΩ DM pull-up resistor

• RPD_DP_EN activates the 15kΩ DP pull-down resistor

• RPD_DM_EN activates the 15kΩ DM pull-down resistor

• HSTERM_EN activates the 45Ω DP and DM high speed termination resistors

TABLE 6-8:

DP/DM TERMINATION VS. SIGNALING MODE

Signaling Mode

Resistor Settings

General Settings

Tri-State Drivers

XXb

01b

0b0b0b0b0b

Power-up or Vbus < VSESSEND

01b

00b1b

0b0b1b1b0b

Host Settings

Host Chirp

00b

10b1b

0b0b1b1b1b

Host Hi-Speed

00b

00b1b

0b0b1b1b1b

Host Full Speed

X1b

00b1b

0b0b1b1b0b

Host HS/FS Suspend

01b

00b1b

0b0b1b1b0b

Host HS/FS Resume

01b

10b1b

0b0b1b1b0b

USB3300 数据表(PDF) 33 Page - Microchip Technology

USB3300 数据表(HTML) 33 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

数据表下载

链接网址

USB3300 数据表(PDF) 33 Page - Microchip Technology

USB3300 数据表(HTML) 33 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

数据表 下载

链接网址

数据表下载