USB3300 datasheet(34/53 Pages) MICROCHIP

34 / 53 page

USB3300

DS00001783B-page 34

 2014-2015 Microchip Technology Inc.

6.2.3

BIAS GENERATOR

This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the

analog circuits. This block requires an external 12K

Ω, 1% tolerance, external reference resistor connected from RBIAS

to ground.

6.3

Crystal Oscillator and PLL

The USB3300 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference clock that is

used by the PHY during both transmit and receive. The USB3300 requires a clean 24MHz crystal or clock as a frequency

reference. If the 24MHz reference is noisy or off frequency the PHY may not operate correctly.

The USB3300 can use either a crystal or an external clock oscillator for the 24MHz reference. The crystal is connected

to the XI and XO pins as shown in the application diagram, Figure 7-1. If a clock oscillator is used the clock should be

connected to the XI input and the XO pin left floating. When a external clock is used the XI pin is designed to be driven

with a 0 to 3.3 volt signal. When using an external clock the user needs to take care to ensure the external clock source

is clean enough to not corrupt the high speed eye performance.

Once the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz clock. The

USB3300 is guaranteed to start the clock within the time specified in Table 5-2, "Electrical Characteristics: CLKOUT

Start-Up". The USB3300 does not support using an external 60MHz clock input.

Host low Speed

10b

00b1b

0b0b1b1b0b

Host LS Suspend

10b

00b

Host LS Resume

10b

10b1b

0b0b1b1b0b

Host Test J/Test_K

00b

10b1b

0b0b1b1b1b

Peripheral Settings

Peripheral Chirp

00b

10b

Peripheral HS

00b

Peripheral FS

01b

00b

Peripheral HS/FS Suspend

01b

00b

Peripheral HS/FS Resume

01b

10b

Peripheral LS

10b

00b

Peripheral LS Suspend

10b

00b

Peripheral LS Resume

10b

Peripheral Test J/Test K

00b

10b

OTG device, Peripheral Chirp

00b

10b

OTG device, Peripheral HS

00b

OTG device, Peripheral FS

01b

00b

OTG device, Peripheral HS/FS Suspend

01b

00b

OTG device, Peripheral HS/FS Resume

01b

10b

OTG device, Peripheral Test J/Test K

00b

10b

Note:

This is the same as Table 40, Section 4.4 of the ULPI 1.1 specification.

TABLE 6-8:

DP/DM TERMINATION VS. SIGNALING MODE (CONTINUED)

Signaling Mode

Resistor Settings

USB3300 数据表(PDF) 34 Page - Microchip Technology

USB3300 数据表(HTML) 34 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

数据表下载