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A6985F 数据表(PDF) 45 Page - STMicroelectronics |
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A6985F 数据表(HTML) 45 Page - STMicroelectronics |
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45 / 77 page  DocID027738 Rev 2 45/77 A6985F Application notes 77 7 Application notes 7.1 Output voltage adjustment In A6985F3V3 and A6985F5V the output voltage is fixed by an internal divider GDIV INT (see Table 5 on page 8). In A6985F the internal reference is equal to 0.85 V typical, and the output voltage is adjusted accordingly to Equation 41 (see Figure 32): Equation 41 where Cr1 capacitor is sometimes useful to increase the small signal phase margin (please refer to Section 6.5: Compensation network design). Figure 32. A6985F application circuit 7.2 Switching frequency A resistor connected to the FSW pin features the selection of the switching frequency. The pinstrapping is performed at power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven floating in order to minimize the quiescent current from VIN. Please refer toTable 6: fSW selection on page 11 to identify the pull-up / pull-down resistor value. fSW = 250 kHz / fSW = 500 kHz preferred codifications don't require any external resistor. VOUT VREF 1 R1 R2 ------- + 0.85 1 R1 R2 ------- + = = |
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