L7292 datasheet(23/60 Pages) STMICROELECTRONICS

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L7292

I2C interface

8.1

Description

This device features an I2C interface and can be operated from a VDD power supply. The

I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The

devices carry a built-in 7-bit device type identifier code in accordance with the I2C bus

definition. The device behaves as a slave in the I2C protocol, with all operations

synchronized by the serial clock. Read and Write operations are initiated by a Start

condition, generated by the bus master. The Start condition is followed by a device select

code and a Read/Write bit (RW), terminated by an acknowledge bit. When writing data to

the device, the device inserts an acknowledge bit during the 9th bit time, following the bus

master's 8-bit transmission. When data is read by the bus master, the bus master

acknowledges the receipt of the data byte in the same way. Data transfers are terminated by

a Stop condition after an ACK for Write and after a NoACK for Read.

8.2

Signal description

8.2.1

Serial clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this

signal is used by slave devices to synchronize the bus to a slower clock, the bus master

must have an open drain output, and a pull-up resistor must be connected from the serial

clock (SCL) to VDD. In most applications, though, this method of synchronization is not

employed, and so the pull-up resistor is not necessary, provided that the bus master has

a push-pull (rather than open drain) output.

8.2.2

Serial data (SDA)

This bidirectional signal is used to transfer data in or out of the device. It is an open drain

output that may be wire-OR'ed with other open drain or open collector signals on the bus.

A pull-up resistor must be connected from serial data (SDA) to VDD.

Figure 5. I2C Start and Stop conditions

L7292 数据表(PDF) 23 Page - STMicroelectronics