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L7292 数据表(PDF) 40 Page - STMicroelectronics |
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L7292 数据表(HTML) 40 Page - STMicroelectronics |
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40 / 60 page ![]() Buck regulator description L7292 40/60 DocID028601 Rev 1 Figure 14. Block diagram The MODA and MODB status is latched inside the L7292 device when SUP ≥ 2.8 V and VBUS is > 70% of its min. value (70% of 1.72 V). After that the EEPROM is read and the wanted power up sequence enabled. 11.2 VOUT selection By writing the PSRxVLEN (bit 7) = 1 in the register: PSR1VL for BUCK1 PSR2VL for BUCK2 PSR3VL for BUCK3 PSR4VL for BUCK4 PSR5VL for BUCK5 It is possible to change the default output voltage of each regulator. This operation disables the MODA and MODB functionality. |
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