L7292 datasheet(41/60 Pages) STMICROELECTRONICS

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L7292

Buck regulator description

In Table 23 are reported the output voltage ranges selectable by register map bits and the

status when in the DSM mode.

11.3

Regulator sequence programmability

The device offers a wide power-on sequence programmability. For each regulator it is

possible to define the initial status (enable or disable each regulator) and the order in the

power up sequence. Other settings are:

SEQCFG.DLY2 - Delay 2 - delay between two sequence steps



0x0: 0 ms / no delay



0x1: 0.5 ms



0x2: 1.0 ms



0x3: 2.0 ms

SEQCFG.DLY1CFG - Delay 1 - configuration delay before/after power up sequence

configuration



0x0: no delay



0x1: delay before POR rising edge



0x2: delay before starting sequence



0x3: delay before starting sequence and before POR rising edge.

Table 23. VOUT ranges

Regulator

Vout min. [V]

Vout max. [V]

Max. DC

CURRENT [A]

Vout step

[mV]

DSM mode

BUCK1

0.9

1.6

1.0

Off

BUCK2

1.5

2.1

0.8

37.5

Off

BUCK3

0.7

1.3

0.5

BUCK4

0.7

1.3

1.0

Off

BUCK5

0.7

1.3

1.6

Off

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