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C161PI 数据表(PDF) 59 Page - Infineon Technologies AG

部件名 C161PI
功能描述  16-Bit Single-Chip Microcontroller
PDF  82 Pages
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制造商  INFINEON [Infineon Technologies AG]
网页  http://www.infineon.com
标志 INFINEON - Infineon Technologies AG

C161PI 数据表(HTML) 59 Page - Infineon Technologies AG

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&3,
Data Sheet
57
1999-07
AC Characteristics
Multiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
W
A + WC + WF (150 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
ALE high time
W
5
CC
11 +
W
A
–
TCL - 14
+
W
A
–ns
Address setup to ALE
W
6
CC
5 +
W
A
–
TCL - 20
+
W
A
–ns
Address hold after ALE
W
7
CC
15 +
W
A
–
TCL - 10
+
W
A
–ns
ALE falling edge to RD,
WR (with RW-delay)
W
8
CC
15 +
W
A
–
TCL - 10
+
W
A
–ns
ALE falling edge to RD,
WR (no RW-delay)
W
9
CC
-10 +
W
A
–
-10 +
W
A
–ns
Address float after RD,
WR (with RW-delay)
W
10
CC
–
6
–6ns
Address float after RD,
WR (no RW-delay)
W
11
CC
–
31
–
TCL + 6
ns
RD, WR low time
(with RW-delay)
W
12
CC
34 +
W
C
–
2TCL - 16
+
W
C
–ns
RD, WR low time
(no RW-delay)
W
13
CC
59 +
W
C
–
3TCL - 16
+
W
C
–ns
RD to valid data in
(with RW-delay)
W
14
SR
–
22 +
W
C
–
2TCL - 28
+
W
C
ns
RD to valid data in
(no RW-delay)
W
15
SR
–
47 +
W
C
–
3TCL - 28
+
W
C
ns
ALE low to valid data in
W
16
SR
–
49 +
W
A
+
W
C
–
3TCL - 30
+
W
A + WC
ns
Address to valid data in
W
17
SR
–
57 + 2
W
A
+
W
C
–
4TCL - 43
+ 2
W
A + WC
ns
Data hold after RD
rising edge
W
18
SR
0
–
0–ns
Data float after RD
W
19
SR
–
36 +
W
F
–
2TCL - 14
+
W
F
ns



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