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C161PI 数据表(PDF) 61 Page - Infineon Technologies AG |
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C161PI 数据表(HTML) 61 Page - Infineon Technologies AG |
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61 / 82 page ![]() &3, Data Sheet 59 1999-07 Data hold after RdCS W 51 SR 0 – 0–ns Data float after RdCS W 52 SR – 30 + W F – 2TCL - 20 + W F ns Address hold after RdCS, WrCS W 54 CC 30 + W F – 2TCL - 20 + W F –ns Data hold after WrCS W 56 CC 30 + W F – 2TCL - 20 + W F –ns 1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below). Multiplexed Bus (Reduced Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 W A + WC + WF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1 / 2TCL = 1 to 20 MHz Unit min. max. min. max. |
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