数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

C161PI 数据表(PDF) 76 Page - Infineon Technologies AG

部件名 C161PI
功能描述  16-Bit Single-Chip Microcontroller
PDF  82 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  INFINEON [Infineon Technologies AG]
网页  http://www.infineon.com
标志 INFINEON - Infineon Technologies AG

C161PI 数据表(HTML) 76 Page - Infineon Technologies AG

Back Button C161PI Datasheet HTML 72Page - Infineon Technologies AG C161PI Datasheet HTML 73Page - Infineon Technologies AG C161PI Datasheet HTML 74Page - Infineon Technologies AG C161PI Datasheet HTML 75Page - Infineon Technologies AG C161PI Datasheet HTML 76Page - Infineon Technologies AG C161PI Datasheet HTML 77Page - Infineon Technologies AG C161PI Datasheet HTML 78Page - Infineon Technologies AG C161PI Datasheet HTML 79Page - Infineon Technologies AG C161PI Datasheet HTML 80Page - Infineon Technologies AG Next Button
Zoom Inzoom in Zoom Outzoom out
 76 / 82 page
background image
&3,
Data Sheet
74
1999-07
AC Characteristics
CLKOUT and READY (Standard Supply Voltage Range)
(Operating Conditions apply)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min.
max.
min.
max.
CLKOUT cycle time
W
29
CC
40
40
2TCL
2TCL
ns
CLKOUT high time
W
30
CC
14
–
TCL – 6
–
ns
CLKOUT low time
W
31
CC
10
–
TCL – 10
–
ns
CLKOUT rise time
W
32
CC
–
4
–4ns
CLKOUT fall time
W
33
CC
–
4
–4ns
CLKOUT rising edge to
ALE falling edge
W
34
CC
0 +
W
A
10 +
W
A
0 +
W
A
10 +
W
A
ns
Synchronous READY
setup time to CLKOUT
W
35
SR
14
–
14
–
ns
Synchronous READY
hold time after CLKOUT
W
36
SR
4
–
4–ns
Asynchronous READY
low time
W
37
SR
54
–
2TCL +
W
58
–ns
Asynchronous READY
setup time
1)
1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
W
58
SR
14
–
14
–
ns
Asynchronous READY
hold time
1)
W
59
SR
4
–
4–ns
Async. READY hold time
after RD, WR high
(Demultiplexed Bus)
2)
2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2
W
A and WC refer to the next following bus cycle, WF refers to the current bus cycle.
The maximum limit for
W
60 must be fulfilled if the next following bus cycle is READY controlled.
W
60
SR
0
0
+ 2
W
A +
W
C + WF
2)
0
TCL - 20
+ 2
W
A + WC
+
W
F
2)
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com