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C161PI 数据表(PDF) 66 Page - Infineon Technologies AG

部件名 C161PI
功能描述  16-Bit Single-Chip Microcontroller
PDF  82 Pages
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制造商  INFINEON [Infineon Technologies AG]
网页  http://www.infineon.com
标志 INFINEON - Infineon Technologies AG

C161PI 数据表(HTML) 66 Page - Infineon Technologies AG

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&3,
Data Sheet
64
1999-07
AC Characteristics
Demultiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
W
A + WC + WF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min.
max.
min.
max.
ALE high time
W
5
CC
10 +
W
A
–
TCL - 10
+
W
A
–ns
Address setup to ALE
W
6
CC
4 +
W
A
–
TCL - 16
+
W
A
–ns
ALE falling edge to RD,
WR (with RW-delay)
W
8
CC
10 +
W
A
–
TCL - 10
+
W
A
–ns
ALE falling edge to RD,
WR (no RW-delay)
W
9
CC
-10 +
W
A
–-10
+
W
A
–ns
RD, WR low time
(with RW-delay)
W
12
CC
30 +
W
C
–
2TCL - 10
+
W
C
–ns
RD, WR low time
(no RW-delay)
W
13
CC
50 +
W
C
–
3TCL - 10
+
W
C
–ns
RD to valid data in
(with RW-delay)
W
14
SR
–
20 +
W
C
–
2TCL - 20
+
W
C
ns
RD to valid data in
(no RW-delay)
W
15
SR
–
40 +
W
C
–
3TCL - 20
+
W
C
ns
ALE low to valid data in
W
16
SR
–
40 +
W
A + WC
–
3TCL - 20
+
W
A + WC
ns
Address to valid data in
W
17
SR
–
50 +
2
W
A + WC
–
4TCL - 30
+ 2
W
A + WC
ns
Data hold after RD
rising edge
W
18
SR
0
–
0–ns
Data float after RD rising
edge (with RW-delay
1))
W
20
SR
–
26 +
2
W
A + WF
1)
–
2TCL - 14
+ 22
W
A
+
W
F
1)
ns
Data float after RD rising
edge (no RW-delay
1))
W
21
SR
–
10 +
2
W
A + WF
1)
–
TCL - 10
+ 22
W
A
+
W
F
1)
ns
Data valid to WR
W
22
CC
20 +
W
C
–
2TCL - 20
+
W
C
–ns



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