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C161PI 数据表(PDF) 71 Page - Infineon Technologies AG

部件名 C161PI
功能描述  16-Bit Single-Chip Microcontroller
PDF  82 Pages
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制造商  INFINEON [Infineon Technologies AG]
网页  http://www.infineon.com
标志 INFINEON - Infineon Technologies AG

C161PI 数据表(HTML) 71 Page - Infineon Technologies AG

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Data Sheet
69
1999-07
Address hold after
RdCS, WrCS
W
55
CC
-16 +
W
F
–
-16 +
W
F
–ns
Data hold after WrCS
W
57
CC
9 +
W
F
–
TCL - 16
+
W
F
–ns
1) RW-delay and
W
A refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Demultiplexed Bus (Reduced Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
W
A + WC + WF (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.



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