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STRFNFCA 数据表(PDF) 10 Page - STMicroelectronics |
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STRFNFCA 数据表(HTML) 10 Page - STMicroelectronics |
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10 / 74 page  Power management and operating modes STRFNFCA 10/74 Doc ID 023077 Rev 10 Figure 5 shows the power-up sequence for a STRFNFCA device; where, ● t0 is the initial wake-up delay 100 µs (minimum) ● t1 is the minimum interrupt width 10 µs (minimum) ● t2 is the delay for the serial interface selection 250 ns (typical) ● t3 is the HFO setup time (tSU(HFO)) 10 ms (maximum) ● t4 is the VPS ramp-up time 10 ms (maximum by design validation) Note: The Serial Interface is selected after the following falling edge of pin IRQ_IN when leaving from POR or Hibernate state. Table 4 lists the signal configuration used to select the serial communication interface. Table 4. Select serial communication interface selection table Pin Serial interface SSI_0 UART: 0 SPI: 1 SSI_1 UART: 0 SPI: 0 |
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