STM32F479AI datasheet(26/208 Pages) STMICROELECTRONICS

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Functional overview

STM32F479xx

26/208

DocID028010 Rev 2

2.16

Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full

temperature range. The application can then select as system clock either the RC oscillator

or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is

detected, the system automatically switches back to the internal RC oscillator and a

software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing

to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL

clock entry is available when necessary (for example if an indirectly used external oscillator

fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB

buses is 180 MHz while the maximum frequency of the high-speed APB domains is

90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.

The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio

class performance. In this case, the I2S master clock can generate all standard sampling

frequencies from 8 kHz to 192 kHz.

2.17

Boot modes

At startup, boot pins are used to select one out of three boot options:

•

Boot from user Flash

•

Boot from system memory

•

Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory

through a serial interface. Refer to application note AN2606 for details.

2.18

Power supply schemes

•

VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when

enabled), provided externally through VDD pins.

•

VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset

blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.

Note:

VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to

Section 2.19.2). Refer to Table 3 to identify the packages supporting this option.

•

VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when VDD is not present.

•

VDDUSB can be connected either to VDD or an external independent power supply (3.0

to 3.6V) for USB transceivers.

For example, when device is powered at 1.8V, an independent power supply 3.3V can

be connected to VDDUSB. When the VDDUSB is connected to a separated power supply,

it is independent from VDD or VDDA but it must be the last supply to be provided and the

first to disappear.

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