LP38853_15 datasheet(16/30 Pages) TI1

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LP38853

SNVS335E – DECEMBER 2006 – REVISED NOVEMBER 2015

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8.2.2.1.2

Output Capacitor

A minimum output capacitance of 10-µF ceramic is required for stability. The amount of output capacitance can

be increased without limit. The output capacitor must be located less than 1 cm from the OUT pin of the device

and returned to the device ground pin with a clean analog ground.

Only high-quality ceramic types such as X5R or X7R must be used, as the Z5U and Y5F types do not provide

sufficient capacitance over temperature.

Tantalum capacitors also provide stable operation across the entire operating temperature range. However, the

effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum

recommended 10-µF ceramic capacitor at the output allows unlimited capacitance, tantalum or aluminum, to be

added in parallel.

8.2.2.1.3

Bias Capacitor

The capacitor on the bias pin must be at least 1 µF and can be any good-quality capacitor (ceramic is

recommended).

8.2.2.1.4

Set The Output Voltage

According to Table 1, R1 is set to 1.07 k

Ω, R2 is set to 1.78 kΩ.

8.2.2.1.5

Feed Forward Capacitor, CFF

When using a ceramic capacitor for COUT, the typical ESR value may be too small to provide any meaningful

positive phase compensation, FZ, to offset the internal negative phase shifts in the gain loop (see Figure 23 and

Equation 4).

FZ = (1 / (2 × π × COUT × ESR))

(4)

A capacitor placed across the gain resistor R1 provides additional phase margin to improve load transient

response of the device. This capacitor, CFF, in parallel with R1, forms a zero in the loop response given by

Equation 5:

FZ = (1 / (2 × π × CFF × R1))

(5)

For optimum load transient response select CFF so the zero frequency, FZ, falls between 10 kHz and 15 kHz as

shown in Equation 6:

(CFF = (1 / (2 × π × R1 × FZ)

(6)

The phase lead provided by CFF diminishes as the DC gain approaches unity, or VOUT approaches VADJ. This is

because CFF also forms a pole with a frequency shown in Equation 7:

FP = (1 / (2 × π × CFF × (R1 || R2) ))

(7)

NOTE

It is important to note that at higher output voltages, where R1 is much larger than R2, the

pole and zero are far apart in frequency. At lower output voltages the frequency of the

pole and the zero move closer together. The phase lead provided from CFF diminishes

quickly as the output voltage is reduced, and has no effect when VOUT = VADJ. For this

reason, relying on this compensation technique alone is adequate only for higher output

voltages. For the LP38853, the practical minimum VOUT is 0.8 V when a ceramic capacitor

is used for COUT.

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