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LP38853 数据表(PDF) 19 Page - Texas Instruments |
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LP38853 数据表(HTML) 19 Page - Texas Instruments |
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19 / 30 page ![]() VOUT VIN 1 2 3 4 5 CIN COUT 6 7 CSS CBIAS VOUT VIN 1 2 3 4 5 CIN COUT 6 7 CSS CBIAS LP38853 www.ti.com SNVS335E – DECEMBER 2006 – REVISED NOVEMBER 2015 9 Power Supply Recommendations The LP38853 device is designed to operate from an input voltage supply range from 3 V and 5.5 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. An input capacitor of at least 10 μF is required. 10 Layout 10.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitic, and thereby reduces load current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similarly to a thermal plane to spread heat from the LDO device when connected to the PowerPAD. In most applications, this ground plane is necessary to meet thermal requirements. 10.2 Layout Examples Figure 31. LP38853 DDPAK/TO-263 and TO-220 Layout Example Figure 32. LP38853 SO PowerPAD Layout Example Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LP38853 |
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