LP38853_15 datasheet(5/30 Pages) TI1

5 / 30 page

LP38853

www.ti.com

SNVS335E – DECEMBER 2006 – REVISED NOVEMBER 2015

6.4 Thermal Information

LP38853

THERMAL METRIC(1)

KTW (DDPAK/TO-263)

NDZ (TO-220)

DDA (SO PowerPAD)

UNIT

7 PINS

8 PINS

RθJA

Junction-to-ambient thermal resistance

34.3

34.0

48.4

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

37.6

36.4

54.6

°C/W

RθJB

Junction-to-board thermal resistance

25.3

25.0

29.1

°C/W

ψJT

Junction-to-top characterization parameter

6.6

6.3

9.6

°C/W

ψJB

Junction-to-board characterization parameter

24.0

23.6

29.0

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

n/a

4.3

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise specified: VOUT = 0.8 V, VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF,

CBIAS = 1 µF, CSS = open; typical (TYP) limits are for TJ = 25°C only, and minimum (MIN) and maximum (MAX) limits apply

over the junction temperature (TJ) range of –40°C to +125°C. Minimum and Maximum limits are specified through test,

design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for

reference purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS ≤ 4.5 V

(1)

3 V

≤ VBIAS ≤ 5.5 V, 10 mA ≤ IOUT ≤ 3 A

492.5

500

507.5

TJ = 25°C

VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS ≤ 4.5 V

(1)

485

515

VADJ

VADJ accuracy

3 V

≤ VBIAS ≤ 5.5 V, 10 mA ≤ IOUT ≤ 3 A

VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS ≤ 4.5 V

(1)

3 V

≤ VBIAS ≤ 5.5 V,

490

500

510

10 mA

≤ IOUT ≤ 3 A,

0°C

≤ TJ ≤ 125°C

3 V

≤ VBIAS ≤ 5.5 V

0.8

1.2

VOUT

VOUT range

4.5 V

≤ VBIAS ≤ 5.5 V

0.8

1.8

ΔVOUT/ΔVIN

Line regulation, VIN

(2)

VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS

0.04

%/V

ΔVOUT/ΔVBIAS

Line regulation, VBIAS

(2)

3 V

≤ VBIAS ≤ 5.5 V

0.1

%/V

Output voltage load

ΔVOUT/ΔIOUT

10 mA

≤ IOUT ≤ 3 A

0.2

%/A

regulation(3)

IOUT = 3 A, TJ = 25°C

240

300

VDO

Dropout voltage(4)

IOUT = 3 A

450

VOUT = 0.8 V, VBIAS = 3 V

10 mA

≤ IOUT ≤ 3 A

8.5

TJ = 25°C

Quiescent current drawn

VOUT = 0.8 V, VBIAS = 3 V

IGND(IN)

from VIN supply

10 mA

≤ IOUT ≤ 3 A

VEN ≤ 0.5 V, TJ = 25°C

100

μA

VEN ≤ 0.5 V

300

10 mA

≤ IOUT ≤ 3 A, TJ = 25°C

3.8

10 mA

≤ IOUT ≤ 3 A

4.5

Quiescent current drawn

IGND(BIAS)

from VBIAS supply

VEN ≤ 0.5 V, TJ = 25°C

100

170

μA

VEN ≤ 0.5 V

200

(1)

VIN cannot exceed either VBIAS or 4.5 V, whichever value is lower.

(2)

Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

(3)

Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load

to full load.

(4)

Dropout voltage is defined as the input to output voltage differential (VIN – VOUT) where the input voltage is low enough to cause the

output voltage to drop 2% from the nominal value.

Submit Documentation Feedback

Product Folder Links: LP38853

LP38853 数据表(PDF) 5 Page - Texas Instruments

LP38853 数据表(HTML) 5 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

数据表下载

链接网址

LP38853 数据表(PDF) 5 Page - Texas Instruments

LP38853 数据表(HTML) 5 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

数据表 下载

链接网址

数据表下载