PIC16F877ATISLASHML datasheet(122/234 Pages) MICROCHIP

122 / 234 page

PIC16F87XA

DS39582B-page 120

 2003 Microchip Technology Inc.

FIGURE 10-7:

ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT

FIGURE 10-8:

ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST

TABLE 10-7:

REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Start

bit

bit 1

bit 0

bit 8

bit 0

Stop

bit

Start

bit

bit 8

Stop

bit

RC7/RX/DT

Load RSR

Read

RCIF

Word 1

RCREG

Bit 8 = 0, Data Byte

Bit 8 = 1, Address Byte

Note:

This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)

because ADDEN = 1.

(pin)

Start

bit

bit 1

bit 0

bit 8

bit 0

Stop

bit

Start

bit

bit 8

Stop

bit

RC7/RX/DT

Load RSR

Read

RCIF

Word 1

RCREG

Bit 8 = 1, Address Byte

Bit 8 = 0, Data Byte

Note:

This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)

because ADDEN was not updated and still = 0.

(pin)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

0Bh, 8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

R0IF

0000 000x

0000 000u

0Ch

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF TMR1IF

0000 0000

18h

RCSTA

SPEN

RX9

SREN

CREN ADDEN

FERR

OERR

RX9D

0000 000x

1Ah

RCREG

USART Receive Register

0000 0000

8Ch

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE TMR2IE TMR1IE

0000 0000

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—BRGH

TRMT

TX9D

0000 -010

99h

SPBRG

Baud Rate Generator Register

0000 0000

Legend:

= unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

Note

Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.

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