COP688CS datasheet(42/53 Pages) NSC

42 / 53 page

Memory Map (Continued)

Address

Contents

S/ADD REG

xxD6

Port G Input Pins (Read Only)

xxD7

Port I Input Pins (Read Only) (Actually

reads Port F input pins)

xxD8

Port C Data Register

xxD9

Port C Configuration Register

xxDA

Port C Input Pins (Read Only)

xxDB

Reserved for Port C

xxDC

Port D

xxDD to xxDF

Reserved for Port D

xxE0 to xxE5

Reserved for EE Control Registers

xxE6

Timer T1 Autoload Register T1RB Lower

Byte

xxE7

Timer T1 Autoload Register T1RB Upper

Byte

xxE8

ICNTRL Register

xxE9

MICROWIRE/PLUS Shift Register

xxEA

Timer T1 Lower Byte

xxEB

Timer T1 Upper Byte

Address

Contents

S/ADD REG

xxEC

Timer T1 Autoload Register T1RA Lower

Byte

xxED

Timer T1 Autoload Register T1RA Upper

Byte

xxEE

CNTRL Control Register

xxEF

PSW Register

xxF0 to FB

On-Chip RAM Mapped as Registers

xxFC

X Register

xxFD

SP Register

xxFE

B Register

xxFF

S Register

0100–017F

On-Chip 128 RAM Bytes

0200–027F

On-Chip 128 RAM Bytes (Reads as

undefined data on COP8SGE)

0300–037F

On-Chip 128 RAM Bytes (Reads as

undefined data on COP8SGE)

Note: Reading memory locations 0070H–007FH (Segment 0) will return all

ones. Reading unused memory locations 0080H–00AFH (Segment 0)

will return undefined data. Reading memory locations from other Seg-

ments (i.e., Segment 2, Segment 3, … etc.) will return undefined data.

Addressing Modes

There are ten addressing modes, six for operand addressing

and four for transfer of control.

OPERAND ADDRESSING MODES

This is the “normal” addressing mode. The operand is the

data memory addressed by the B pointer or X pointer.

decrement of pointer)

This addressing mode is used with the LD and X instruc-

tions. The operand is the data memory addressed by the B

pointer or X pointer. This is a register indirect mode that au-

tomatically post increments or decrements the B or X regis-

ter after executing the instruction.

Direct

The instruction contains an 8-bit address field that directly

points to the data memory for the operand.

Immediate

The instruction contains an 8-bit immediate field as the oper-

and.

Short Immediate

This addressing mode is used with the Load B Immediate in-

struction. The instruction contains a 4-bit immediate field as

the operand.

Indirect

This addressing mode is used with the LAID instruction. The

contents of the accumulator are used as a partial address

(lower 8 bits of PC) for accessing a data operand from the

program memory.

TRANSFER OF CONTROL ADDRESSING MODES

Relative

This mode is used for the JP instruction, with the instruction

field being added to the program counter to get the new pro-

gram location. JP has a range from −31 to +32 to allow a

1-byte relative jump (JP + 1 is implemented by a NOP in-

struction). There are no “pages” when using JP, since all 15

bits of PC are used.

Absolute

This mode is used with the JMP and JSR instructions, with

the instruction field of 12 bits replacing the lower 12 bits of

the program counter (PC). This allows jumping to any loca-

tion in the current 4k program memory segment.

Absolute Long

This mode is used with the JMPL and JSRL instructions, with

the instruction field of 15 bits replacing the entire 15 bits of

the program counter (PC). This allows jumping to any loca-

tion up to 32k in the program memory space.

Indirect

This mode is used with the JID instruction. The contents of

the accumulator are used as a partial address (lower 8 bits of

PC) for accessing a location in the program memory. The

contents of this program memory location serve as a partial

address (lower 8 bits of PC) for the jump to the next instruc-

tion.

Note: The VIS is a special case of the Indirect Transfer of Control addressing

mode, where the double byte vector associated with the interrupt is

transferred from adjacent addresses in the program memory into the

program counter (PC) in order to jump to the associated interrupt ser-

vice routine.

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