COP688CS datasheet(19/53 Pages) NSC

19 / 53 page

CONTROL REGISTERS (Continued)

ICNTRL Register (Address X'00E8)

Reserved

LPEN

T0PND

T0EN

µWPND

µWEN

T1PNDB

T1ENB

Bit 7

Bit 0

The ICNTRL register contains the following bits:

Reserved This bit is reserved and should be zero

LPEN

L Port Interrupt Enable (Multi-Input Wakeup/

Interrupt)

T0PND

Timer T0 Interrupt pending

T0EN

Timer T0 Interrupt Enable (Bit 12 toggle)

µWPND

MICROWIRE/PLUS interrupt pending

µWEN

Enable MICROWIRE/PLUS interrupt

T1PNDB

Timer T1 Interrupt Pending Flag for T1B cap-

ture edge

T1ENB

Timer T1 Interrupt Enable for T1B Input cap-

ture edge

T2CNTRL Register (Address X'00C6)

T2C3

T2C2

T2C1

T2C0

T2PNDA

T2ENA

T2PNDB

T2ENB

Bit 7

Bit 0

The T2CNTRL control register contains the following bits:

T2C3

Timer T2 mode control bit

T2C2

Timer T2 mode control bit

T2C1

Timer T2 mode control bit

T2C0

Timer

Start/Stop

control

timer

modes 1 and 2, T2 Underflow Interrupt Pend-

ing Flag in timer mode 3

T2PNDA

Timer T2 Interrupt Pending Flag (Autoreload

RA in mode 1, T2 Underflow in mode 2, T2A

capture edge in mode 3)

T2ENA

Timer T2 Interrupt Enable for Timer Underflow

or T2A Input capture edge

T2PNDB

Timer T2 Interrupt Pending Flag for T2B cap-

ture edge

T2ENB

Timer T2 Interrupt Enable for Timer Underflow

or T2B Input capture edge

Note: The T2CNTRL register is not available on the CS series.

T3CNTRL Register (Address X'00B6)

T3C3

T3C2

T3C1

T3C0

T3PNDA

T3ENA

T3PNDB

T3ENB

Bit 7

Bit 0

The T3CNTRL control register contains the following bits:

T3C3

Timer T3 mode control bit

T3C2

Timer T3 mode control bit

T3C1

Timer T3 mode control bit

T3C0

Timer

Start/Stop

control

timer

modes 1 and 2, T3 Underflow Interrupt Pend-

ing Flag in timer mode 3

T3PNDA

Timer T3 Interrupt Pending Flag (Autoreload

RA in mode 1, T3 Underflow in mode 2, T3A

capture edge in mode 3)

T3ENA

Timer T3 Interrupt Enable for Timer Underflow

or T3A Input capture edge

T3PNDB

Timer T3 Interrupt Pending Flag for T3B cap-

ture edge

T3ENB

Timer T3 Interrupt Enable for Timer Underflow

or T3B Input capture edge

Note: The T3CNTRL regoster os mpt avao;ab;e pm tje CS series.

Timers

These devices contain a very versatile set of timers (T0, T1,

T2, T3 for all except the CS series, which only use T0 and

T1). All timers and associated autoreload/capture registers

power up containing random data.

TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining

real time and low power with the IDLE mode. This IDLE

mode support is furnished by the IDLE timer T0, which is a

16-bit timer. The Timer T0 runs continuously at the fixed rate

of the instruction cycle clock, t

c. The user cannot read or

write to the IDLE Timer T0, which is a count down timer.

The Timer T0 supports the following functions:

j Exit out of the Idle Mode (See Idle Mode description)

j WATCHDOG logic (See WATCHDOG description)

j Start up delay out of the HALT mode

The IDLE Timer T0 can generate an interrupt when the thir-

teenth bit toggles. This toggle is latched into the T0PND

pending flag, and will occur every 4 ms at the maximum

clock frequency (t

c = 1 µs). A control flag T0EN allows the in-

terrupt from the thirteenth bit of Timer T0 to be enabled or

disabled. Setting T0EN will enable the interrupt, while reset-

ting it will disable the interrupt.

TIMER T1, TIMER T2 AND TIMER T3

These devices can have a set of up to three powerful timer/

counter blocks, T1, T2 and T3. The associated features and

functioning of a timer block are described by referring to the

timer block Tx. Since the three timer blocks, T1, T2 and T3

are identical, all comments are equally applicable to any of

the three timer blocks.

Each timer block consists of a 16-bit timer, Tx, and two sup-

porting 16-bit autoreload/capture registers, RxA and RxB.

Each timer block has two pins associated with it, TxA and

TxB. The pin TxA supports I/O required by the timer block,

while the pin TxB is an input to the timer block. The powerful

and flexible timer block allows the device to easily perform all

timer functions with minimal software overhead. The timer

block has three operating modes: Processor Independent

PWM mode, External Event Counter mode, and Input Cap-

ture mode.

The control bits TxC3, TxC2, and TxC1 allow selection of the

different modes of operation.

Mode 1. Processor Independent PWM Mode

As the name suggests, this mode allows the device to gen-

erate a PWM signal with very minimal user intervention. The

user only has to define the parameters of the PWM signal

(ON time and OFF time). Once begun, the timer block will

continuously generate the PWM signal completely indepen-

dent of the microcontroller. The user software services the

timer block only when the PWM parameters require updat-

ing.

In this mode the timer Tx counts down at a fixed rate of t

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, RxA and RxB. The very

first underflow of the timer causes the timer to reload from

the register RxA. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the

timer for PWM mode operation.

Figure 8 shows a block diagram of the timer in PWM mode.

COP688CS 数据表(PDF) 19 Page - National Semiconductor (TI)

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