COP688CS datasheet(16/53 Pages) NSC

16 / 53 page

Pin Descriptions (Continued)

phase of the SK clock. The G7 configuration bit, if set high,

enables the clock start up delay after HALT when the R/C

clock configuration is used.

Config Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

G6 SI (MICROWIRE Serial Data Input)

G5 SK (MICROWIRE Serial Clock)

G4 SO (MICROWIRE Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

G0 INTR (External Interrupt Input)

Port G has the following dedicated functions:

G7 CKO Oscillator dedicated output or general purpose

input

G1 WDOUT WATCHDOG and/or Clock Monitor dedi-

cated output

Port C is an 8-bit I/O port. The 40-pin device does not have

a full complement of Port C pins. The unavailable pins are

not terminated. A read operation for these unterminated pins

will return unpredicatable values.

Port I is an eight-bit Hi-Z input port.

Port I1–I3 are used for Comparator 1. Port I4–I6 are used for

Comparator 2.

The Port I has the following alternate features:

COMP2OUT (Comparator 2 Output)

COMP2+IN (Comparator 2 Positive Input)

COMP2−IN (Comparator 2 Negative Input)

COMP1OUT (Comparator 1 Output)

COMP1+IN (Comparator 1 Positive Input)

COMP1−IN (Comparator 1 Negative Input)

Port D is an 8-bit output port that is preset high when RESET

goes low. The user can tie two or more D port outputs (ex-

cept D2) together in order to get a higher drive.

Functional Description

The architecture of the device is modified Harvard architec-

ture. With the Harvard architecture, the control store pro-

gram memory (ROM) is separated from the data store

memory (RAM). Both ROM and RAM have their own sepa-

rate addressing space with separate address buses. The ar-

chitecture, though based on Harvard architecture, permits

transfer of data from ROM to RAM.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t

c) cycle time.

There are six CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). The SP is initialized to RAM ad-

dress 06F with reset.

S is the 8-bit Data Segment Address Register used to extend

the lower half of the address range (00 to 7F) into 256 data

segments of 128 bytes each.

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

PROGRAM MEMORY

The program memory consists of up to 24 kbytes of ROM.

These bytes may hold program instructions or constant data

(data tables for the LAID instruction, jump vectors for the JID

instruction, and interrupt vectors for the VIS instruction). The

program memory is addressed by the 15-bit program

counter (PC). All interrupts in the devices vector to program

memory location 0FF Hex.

DATA MEMORY

The data memory address space includes the on-chip RAM

and data registers, the I/O registers (Configuration, Data and

Pin), the control registers, the MICROWIRE/PLUS SIO shift

with the timers (with the exception of the IDLE timer). Data

memory is addressed directly by the instruction or indirectly

by the B, X, SP pointers and S register.

The data memory consists of up to 512 bytes of RAM. Six-

teen bytes of RAM are mapped as “registers” at addresses

0F0 to 0FF Hex. These registers can be loaded immediately,

and also decremented and tested with the DRSZ (decrement

registers X, SP, B and S are memory mapped into this space

at address locations 0FC to 0FF Hex respectively, with the

other registers being available for general usage.

The instruction set permits any bit in memory to be set, reset

or tested. All I/O and registers (except A and PC) are

memory mapped; therefore, I/O bits and register bits can be

directly and individually set, reset and tested. The accumula-

tor (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

Data Memory Segment RAM

Extension

Data memory address 0FF is used as a memory mapped lo-

cation for the Data Segment Address Register (S).

The data store memory is either addressed directly by a

single byte address within the instruction, or indirectly rela-

tive to the reference of the B, X, or SP pointers (each con-

tains a single-byte address). This single-byte address allows

an addressing range of 256 locations from 00 to FF hex. The

upper bit of this single-byte address divides the data store

memory into two separate sections as outlined previously.

With the exception of the RAM register memory from ad-

dress locations 00F0 to 00FF, all RAM memory is memory

mapped with the upper bit of the single-byte address being

equal to zero. This allows the upper bit of the single-byte ad-

dress to determine whether or not the base address range

(from 0000 to 00FF) is extended. If this upper bit equals one

(representing address range 0080 to 00FF), then address

extension does not take place. Alternatively, if this upper bit

equals zero, then the data segment extension register S is

used to extend the base address range (from 0000 to 007F)

from XX00 to XX7F, where XX represents the 8 bits from the

S register. Thus the 128-byte data segment extensions are

located from addresses 0100 to 017F for data segment 1,

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