COP8SA datasheet(39/60 Pages) NSC

39 / 60 page

12.0 Memory Map

All RAM, ports and registers (except A and PC) are mapped into data memory address space.

RAM

Address

Contents

Select

ADD REG

64 On-Chip RAM Bytes.

02 to 2F

On-Chip RAM (48 Bytes)

(COP8SAAx)

30 to 7F

Unused RAM (Reads as all ones)

128 On-Chip RAM Bytes

00 to 6F

On-Chip RAM (112 Bytes)

(COP8SABx/SACx)

70 to 7F

Unused RAM (Reads as all ones)

80 to 93

Reserved

Port F Data Register

Port F Configuration Register

Port F Input Pins (Read Only)

Reserved

A0 to C6

Reserved

WATCHDOG Service Register (Reg: WDSVR)

MIWU Edge Select Register (Reg: WKEDG)

MIWU Enable Register (Reg: WKEN)

MIWU Pending Register (Reg: WKPND)

CB to CF

Reserved

Port L Data Register

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved

Port G Data Register

Port G Configuration Register

Port G Input Pins (Read Only)

Reserved

Port C Data Register

Port C Configuration Register

Port C Input Pins (Read Only)

Reserved

Port D

DD to DF

Reserved

E0 to E5

Reserved

Timer T1 Autoload Register T1RB Lower Byte

Timer T1 Autoload Register T1RB Upper Byte

ICNTRL Register

MICROWIRE/PLUS Shift Register

Timer T1 Lower Byte

Timer T1 Upper Byte

Timer T1 Autoload Register T1RA Lower Byte

Timer T1 Autoload Register T1RA Upper Byte

CNTRL Control Register

PSW Register

F0 to FB

On-Chip RAM Mapped as Registers

X Register

SP Register

B Register

Reserved (Segment Register)

Reading any undefined memory location in the address range of 0080H–00FFH will return undefined data.

COP8SA 数据表(PDF) 39 Page - National Semiconductor (TI)

COP8SA 数据表(HTML) 39 Page - National Semiconductor (TI)

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COP8SA 数据表(PDF) 39 Page - National Semiconductor (TI)

COP8SA 数据表(HTML) 39 Page - National Semiconductor (TI)

Html Pages

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