COP8SA datasheet(8/60 Pages) NSC

8 / 60 page

AC Electrical Characteristics

0˚C

≤ T

A ≤ +70˚C unless otherwise specified.

Parameter

Conditions

Min

Typ

Max

Units

Instruction Cycle Time (t

Crystal/Resonator, External

4.5V

≤ V

CC ≤ 5.5V

1.0

µs

2.7V

≤ V

CC < 4.5V

2.0

µs

Internal R/C Oscillator

4.5V

≤ V

CC ≤ 5.5V

2.0

µs

2.7V

≤ V

CC < 4.5V

TBD

µs

R/C Oscillator Frequency Variation

4.5V

≤ V

CC ≤ 5.5V

±35

(Note 8)

2.7V

≤ V

CC < 4.5V

TBD

External CKI Clock Duty Cycle (Note 8)

fr = Max

Rise Time (Note 8)

fr = 10 MHz Ext Clock

Fall Time (Note 8)

fr = 10 MHz Ext Clock

Inputs

SETUP

4.5V

≤ V

CC ≤ 5.5V

200

2.7V

≤ V

CC < 4.5V

500

HOLD

4.5V

≤ V

CC ≤ 5.5V

2.7V

≤ V

CC < 4.5V

150

Output Propagation Delay (Note 7)

L = 2.2k, CL = 100 pF

PD1,tPD0

SO, SK

4.5V

≤ V

CC ≤ 5.5V

0.7

µs

2.7V

≤ V

CC < 4.5V

1.75

µs

All Others

4.5V

≤ V

CC ≤ 5.5V

1.0

µs

2.7V

≤ V

CC < 4.5V

2.5

µs

MICROWIRE Setup Time (t

UWS) (Note 7)

MICROWIRE Hold Time (t

UWH) (Note 7)

MICROWIRE Output Propagation Delay (t

UPD)

220

MICROWIRE Maximum Shift Clock

Master Mode

500

kHz

Slave Mode

MHz

Input Pulse Width (Note 7)

Interrupt Input High Time

Interrupt Input Low Time

Timer 1 Input High Time

Timer 1 Input Low Time

Reset Pulse Width

µs

Note 2: tC = Instruction cycle time (Clock input frequency divided by 10).

Note 3: Maximum rate of voltage change must be < 0.5 V/ms.

Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC

and outputs driven low but not connected to a load.

Note 5: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal

or external configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5 pro-

grammed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; WATCHDOG and clock monitor disabled.

Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.

Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when

biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two

pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-

cludes ESD transients.

Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 8: Parameter characterized but not tested.

Note 9: Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.

COP8SA 数据表(PDF) 8 Page - National Semiconductor (TI)

COP8SA 数据表(HTML) 8 Page - National Semiconductor (TI)

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COP8SA 数据表(PDF) 8 Page - National Semiconductor (TI)

COP8SA 数据表(HTML) 8 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表 下载

链接网址

数据表下载