COP8SA datasheet(17/60 Pages) NSC

17 / 60 page

6.0 Functional Description (Continued)

6.7 RESET

The device is initialized when the RESET pin is pulled low or

the On-chip Power-On Reset is enabled.

The following occurs upon initialization:

Port L: TRISTATE

Port C: TRISTATE

Port G: TRISTATE

Port F: TRISTATE

Port D: HIGH

PC: CLEARED to 0000

PSW, CNTRL and ICNTRL registers: CLEARED

SIOR: UNAFFECTED after RESET with power already

applied

RANDOM after RESET at power-on

T1CNTRL: CLEARED

Accumulator, Timer 1:

RANDOM after RESET with crystal clock option

(power already applied)

UNAFFECTED after RESET with R/C clock option

(power already applied)

RANDOM after RESET at power-on

WKEN, WKEDG: CLEARED

WKPND: RANDOM

SP (Stack Pointer):

Initialized to RAM address 02F Hex (devices with

64 bytes of RAM), or initialized to

RAM address 06F Hex (devices with

128 bytes of RAM).

B and X Pointers:

UNAFFECTED after RESET with power

already applied

RANDOM after RESET at power-on

RAM:

UNAFFECTED after RESET with power already

applied

RANDOM after RESET at power-on

WATCHDOG (if enabled):

The device comes out of reset with both the WATCHDOG

logic and the Clock Monitor detector armed, with the

WATCHDOG service window bits set and the Clock Monitor

bit set. The WATCHDOG and Clock Monitor circuits are in-

hibited during reset. The WATCHDOG service window bits

being initialized high default to the maximum WATCHDOG

service window of 64k t

C clock cycles. The Clock Monitor bit

being initialized high will cause a Clock Monitor error follow-

ing reset if the clock has not reached the minimum specified

frequency at the termination of reset. A Clock Monitor error

will cause an active low error output on pin G1. This error

output will continue until 16 t

C–32 tC clock cycles following

the clock frequency reaching the minimum specified value,

at which time the G1 output will go high.

6.7.1 External Reset

The RESET input when pulled low initializes the device. The

RESET pin must be held low for a minimum of one instruc-

tion cycle to guarantee a valid reset. During Power-Up initial-

ization, the user must ensure that the RESET pin is held low

until the device is within the specified V

CC voltage. An R/C

circuit on the RESET pin with a delay 5 times (5x) greater

than the power supply rise time or 15 µs whichever is

greater, is recommended. Reset should also be wide enough

to ensure crystal start-up upon Power-Up.

RESET may also be used to cause an exit from the HALT

mode.

A recommended reset circuit for this deviced is shown in

Fig-

ure 9.

6.7.2 On-Chip Power-On Reset

The on-chip reset circuit is selected by a bit in the ECON reg-

ister. When enabled, the device generates an internal reset

as V

CC rises to a voltage level above 2.0V. The on-chip reset

circuitry is able to detect both fast and slow rise times on V

CC rise time between 10 ns and 50 ms).

Under no circumstances should the RESET pin be allowed

to float. If the on-chip Power-On Reset feature is being used,

RESET pin should be connected directly to V

CC. The output

of the power-on reset detector will always preset the Idle

timer to 0FFF(4096 t

C). At this time, the internal reset will be

generated.

If the Power-On Reset feature is enabled, the internal reset

will not be turned off until the Idle timer underflows. The inter-

nal reset will perform the same functions as external reset.

The user is responsible for ensuring that V

CC is at the mini-

mum level for the operating frequency within the 4096 t

C. Af-

ter the underflow, the logic is designed such that no addi-

tional internal resets occur as long as V

CC remains above

2.0V.

Note: While the POR feature of the COP8SAx was never intended to function

as a brownout detector, there are certain constraints of this block that

the system designer must address to properly recover from a brownout

condition. This is true regardless of whether the internal POR or the

external reset feature is used.

A brownout condition is reached when VCC of the device goes below

the minimum operating conditions of the device. The minimum guaran-

teed operating conditions are defined as VCC = 4.5V @ 10 MHz CKI,

VCC = 2.7V @ 4 MHz, or VCC = 2.0V during HALT mode (or when CKI

is stopped) operation.

When using either the external reset or the POR feature to recover

from a brownout condition, VCC must be lowered to 0.25V or an exter-

nal reset must be applied whenever it goes below the minimum oper-

ating conditions as stated above.

DS012838-13

FIGURE 8. Reset Logic

DS012838-14

RC >5x power supply rise time or 15 µs, whichever is greater.

FIGURE 9. Reset Circuit Using External Reset

COP8SA 数据表(PDF) 17 Page - National Semiconductor (TI)

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