ADS5541IPAPR datasheet(25/37 Pages) TI1

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CLOCK INPUT

0.01

µF

CLKP

CLKM

0.01

µF

Differential Square Wave

or Sine Wave

(3V

PP)

ADS5541

5 kW

3 pF

6 pF

CLKP

CLKM

Clock Duty Cycle (%)

fIN = 20MHz

SNR

SFDR

0.01

µF

0.01

µF

CLKP

CLKM

Square Wave

or Sine Wave

(3V

PP)

ADS5541

Production Data

ADS5541

SBAS307C – MAY 2004 – REVISED FEBRUARY 2007

The ADS5541 clock input can also be driven

differentially,

reducing

susceptibility

The ADS5541 clock input can be driven with either a

common-mode noise. In this case, it is best to

differential clock signal or a single-ended clock input,

connect both clock inputs to the differential input

with little or no difference in performance between

clock signal with 0.01

µF capacitors, as shown in

both configurations. The common-mode voltage of

Figure 47.

the clock inputs is set internally to CM (pin 17) using

internal 5k

Ω resistors that connect CLKP (pin 10)

and CLKM (pin 11) to CM (pin 17), as shown in

Figure 45.

Figure 47. AC-Coupled, Differential Clock Input

For

high-input

frequency

sampling,

recommended to use a clock source with low jitter.

Additionally, the internal ADC core uses both edges

of the clock for the conversion process. This means

that, ideally, a 50% duty cycle should be provided.

Figure 48 shows the performance variation of the

ADC versus clock duty cycle.

Figure 45. Clock Inputs

When driven with a single-ended CMOS clock input,

it is best to connect CLKM (pin 11) to ground with a

0.01

µF capacitor, while CLKP is ac-coupled with a

0.01

µF capacitor to the clock source, as shown in

Figure 46.

Figure 48. AC Performance vs Clock Duty Cycle

Figure 46. AC-Coupled, Single-Ended Clock Input

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