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ADS5541IPAPR 数据表(PDF) 27 Page - Texas Instruments

部件名 ADS5541IPAPR
功能描述  14-Bit, 105MSPS Analog-To-Digital Converter
PDF  37 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

ADS5541IPAPR 数据表(HTML) 27 Page - Texas Instruments

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Production Data
ADS5541
SBAS307C – MAY 2004 – REVISED FEBRUARY 2007
The timing characteristics of the digital outputs
To use the input clock as the data capture clock, it is
change for sampling rates below the 105MSPS
necessary to delay the input clock by a delay, td, that
maximum sampling frequency. Table 5 and Table 6
results in the desired setup or hold time. Use either
show the setup, hold, and input clocks to output data
of the following equations to calculate the value of tD.
delays, and rise and fall times for different sampling
Desired setup time = tD– tSTART
frequencies with the DLL on and off, respectively.
Desired hold time = tEND – tD
Table 7 and Table 8 show the values of various
timing parameters for lower sampling frequencies,
both with DLL on and off.
Table 5. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
tSU (ns)
tH (ns)
tSTART (ns)
tEND (ns)
tR (ns)
tF (ns)
fS
(MSPS)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
80
2.8
3.7
2.8
3.3
0.5
1.7
5.3
7.9
5.8
6.6
4.4
5.3
65
3.8
4.6
3.6
4.1
–0.5
0.8
5.3
8.5
6.7
7.2
5.5
6.4
Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
tSU (ns)
tH (ns)
tSTART (ns)
tEND (ns)
tR (ns)
tF (ns)
fS
(MSPS)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
80
3.2
4.2
1.8
3
3.8
5
8.4
11
5.8
6.6
4.4
5.3
65
4.3
5.7
2
3
2.8
4.5
8.3
11.8
6.6
7.2
5.5
6.4
40
8.5
11
2.6
3.5
–1
1.5
8.9
14.5
7.5
8
7.3
7.8
20
17
25.7
2.5
4.7
–9.8
2
9.5
21.6
7.5
8
7.6
8
10
27
51
4
6.5
-30
-3
11.5
31
2
284
370
8
19
185
320
515
576
50
82
75
150
Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
CLKOUT
CLKOUT
CLKOUT Jitter, Peak-to-Peak
Input-to-Output Clock Delay
tRISE (ns)
tFALL (ns)
tJIT (ps)
tPDI (ns)
fS
(MSPS)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
80
2.5
2.8
2.1
2.3
210
315
3.7
4.3
5.1
65
3.1
3.5
2.6
2.9
260
380
3.5
4.1
4.8
Table 8. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
CLKOUT Jitter,
CLKOUT
CLKOUT
Peak-to-Peak
Input-to-Output Clock Delay
tRISE (ns)
tFALL (ns)
tJIT (ps)
tPDI (ns)
fS
(MSPS)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
80
2.5
2.8
2.1
2.3
210
315
7.1
8
8.9
65
3.1
3.5
2.6
2.9
260
380
7.8
8.5
9.4
40
4.8
5.3
4
4.4
445
650
9.5
10.4
11.4
20
8.3
9.5
7.6
8.2
800
1200
13
15.5
18
2
31
52
36
65
2610
4400
537
551
567
27
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