ADS5541IPAPR datasheet(9/37 Pages) TI1

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DFS t

DD t VDFS t

DFS u

Production Data

ADS5541

SBAS307C – MAY 2004 – REVISED FEBRUARY 2007

Table 2. Serial Register Table(1)

D11

D10

DESCRIPTION

DLL

Clock DLL

CTRL

Internal DLL is on; recommended for 60MSPS to 105MSPS

clock speeds.

Internal DLL is off; recommended for 2MSPS to 80MSPS

clock speeds.

TP<1>

TP<0>

Test Mode

Normal mode of operation

All outputs forced to 0

All outputs forced to 1

Each output bit toggles between 0 and 1. (2)(3)

PDN

Power Down

Normal mode of operation

Device is put in power-down (low-current) mode.

(1)

The register contents default to the appropriate setting for normal operation up on RESET.

(2)

The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode

outputs will be the binary two's complement equivalent of these patterns as described in the Output Information section.

(3)

While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0–D13. For

example, when D0 is a 1, D1 is not assured to be a 0, and vice-versa.

Table 3. Data Format Select (DFS) Table

DFS-PIN VOLTAGE (VDFS)

DATA FORMAT

CLOCK OUTPUT POLARITY

Straight Binary

Data valid on rising edge

Two's Complement

Data valid on rising edge

Straight Binary

Data valid on falling edge

Two's Complement

Data valid on falling edge

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