DP8570AV datasheet(8/26 Pages) NSC

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Functional Description (Continued)

The oscillator is programmed via the Real Time Mode Reg-

ister to operate at various frequencies The crystal oscillator

is designed to offer optimum performance at each frequen-

cy Thus at 32768 kHz the oscillator is configured as a low

frequency and low power oscillator At the higher frequen-

cies the oscillator inverter is reconfigured In addition to the

inverter the oscillator feedback bias resistor is included on

chip as shown in

Figure 4 The oscillator input may be driv-

en from an external source if desired Refer to test mode

application note for details The oscillator stability is en-

hanced through the use of an on chip regulated power sup-

ply

The typical range of trimmer capacitor (as shown in Oscilla-

tor Circuit Diagram

Figure 4 and in the typical application) at

the oscillator input pin is suggested only to allow accurate

tuning of the oscillator This range is based on a typical

printed circuit board layout and may have to be changed

depending on the parasitic capacitance of the printed circuit

board or fixture being used In all cases the load capaci-

tance

specified by the crystal manufacturer (nominal value

11 pF for the 32768 crystal) is what determines proper os-

cillation This load capcitance is the series combination of

capacitance on each side of the crystal (with respect to

ground)

TLF8638 – 3

FIGURE 4 Oscillator Circuit Diagram

XTAL

ROUT

(Switched Internally)

3232768 kHz 47 pF 2 pF – 22 pF 150 kX to 350 kX

4194304 MHz 68 pF 0 pF – 80 pF 500X to 900X

49152 MHz

68 pF 29 pF – 49 pF 500X to 900X

INTERRUPT LOGIC FUNCTIONAL DESCRIPTION

The TCP has the ability to coordinate processor timing ac-

tivities To enhance this an interrupt structure has been im-

plemented which enables several types of events to cause

interrupts Interrupts are controlled via two Control Regis-

ters in block 1 and two Status Registers in block 0 (See

Figure 5

and Table I)

The interrupts are enabled by writing a one to the appropri-

ate bits in Interrupt Control Register 0 andor 1 Any of the

interrupts can be routed to either the INTR pin or the MFO

pin depending on how the Interrupt Routing register is pro-

grammed This for example enables the user to dedicate

the MFO as a non-maskable interrupt pin to the CPU for

power failure detection and enable all other interrupts to

appear on the INTR pin The polarity for the active interrupt

can be programmed in the Output Mode Register for either

active high or low and open drain or push pull outputs

TABLE I Registers that are Applicable

to Interrupt Control

Page

Address

Select

Main Status Register

00H

Periodic Flag Register

03H

Interrupt Routing

04H

Interrupt Control

03H

Interrupt Control

04H

Output Mode

02H

The Interrupt Status Flag D0 in the Main Status Register

indicates the state of INTR and MFO outputs It is set when

either output becomes active and is cleared when all TCP

interrupts have been cleared and no further interrupts are

pending (ie both INTR and MFO are returned to their inac-

tive state) This flag enables the TCP to be rapidly polled by

the mP to determine the source of an interrupt in a wired

OR interrupt system

Note that the Interrupt Status Flag will only monitor the state

of the MFO output if it has been configured as an interrupt

output (see Output Mode Register description) This is true

regardless of the state of the Interrupt Routing Register

Thus the Interrupt Status Flag provides a true reflection of

all conditions routed to the external pins

Status for the interrupts are provided by the Main Status

Main Status Register are the main interrupt bits

These register bits will be set when their associated timing

events occur Enabled Alarm or Timer interrupts that occur

will set its Main Status Register bit to a one However an

external interrupt will only be generated if the appropriate

Alarm or Timer interrupt enable bits are set (see

Figure 5 )

Disabling the periodic bits will mask the Main Status Regis-

ter periodic bit but not the Periodic Flag Register bits The

Power Fail Interrupt bit is set when the interrupt is enabled

and a power fail event has occurred and is not reset until

the power is restored If all interrupt enable bits are 0 no

interrupt will be asserted However status still can be read

from the Main Status Register in a polled fashion (see

Fig-

ure 5 )

To clear a flag in bits D2 – D5 of the Main Status Register a 1

must be written back into the bit location that is to be

cleared For the Periodic Flag Register reading the status

will reset all the periodic flags

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